Hi.

I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.

there is some options in makefile such as 

# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…

Hi everyone,

I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

my question sounds trivial, but I just cannot find the register for the program counter in my Cortex-M0. According to the Register TRM it should be R15, which is not available in the GPR module.

Best regards,
LeChuck

//edit: talking about the Verilog…

I saw, and tried in the past already, to simulate the Cortex-M0. It does not really matter efficiency, customization and so on, but only the learning process behind a steup for a correct very basic simulation.

I was trying to setup a Linux machine, when…

Hello together, I am little bit confused regarding to the Cortex-M0DS comparability to Altera FPGAs.

On one hand, according to the information out of the white paper An introduction to ARM Cortex-M0 Design Start it must be possible to run the Cortex-M0…