Warning: It blocks containing 32-bit Thumb instructions are deprecated in ARMv8 with GCC 4.9

Carlos Delfino

Dear colleagues.

I am compiling the Intel TBB in an effort to optimize my code to the Cortex-M53, however, because I was still forced to use GCC 4.9 I'm getting some warning messages about the use of 32bit Thumb Instrucions in IT blocks:

Warning…

Answered

Real Value of PC Register.

Carlos Delfino

I've been reading books on the ARM Cortex-M architecture and as already mentioned in other post, all the books are consistent in saying that the PC points four bytes (Thumb Instruction Set) forward due to Pipeline (prefetch).

Did some testing with…

Answered

[Cortex-M0] Thumb mode & code size

wshen

Hi,

I'm somewhat confused with the Thumb mode code size. My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions. When I compile my Cortex-M0+ project (which should…

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M0+ Stack Pointer (PSP/MSP) Clarification

Sean Dunlevy

Background

I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…

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Linker in gnu arm toolchain says "group ended without start" thought there is no such option in my build

ShyamThella

shyam@shyam:~/projects/zynq/microzed/linux_source/Test_Chips$ make
make -C /home/shyam/projects/zynq/microzed/linux_source/Test_Chips/../dev_tools/build
make[1]: Entering directory `/home/shyam/projects/zynq/microzed/linux_source/dev_tools/build'
Making…

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Store the value of PC to Memory address

Muzahir

I want to store the value of Program Counter(pc) to a memory location.

I did this,

LDR R1, =[0x20000000]

STR R15, [R1,#0]

I got an error saying, "Error: r15(pc) not allowed here -- `str R15,[R1,#0]'.

How should I get over this error?

Answered

Link to download gcc support for TrustZone for ARMv8-M

Diya Soubra

* All GCC 6 features, plus latest mainline features:

+ Full ARMv8-M support including atomics and Security Extensions

+ ARM PURECODE support for ARMv7-M and ARMv8-M Mainline

+ Co-processor intrinsics support

+ Cortex-M23 and Cortex-M33 support

+ -mthumb…

External BRAM as I/D memory for Cortex-M1 DesignStart package for Xilinx FPGAs

mccabecathal

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Answered

over 1 year ago
DesignStart
DesignStart forum

NVIC and ARM asm

martin

Cannot configure interupts of TIM6 on stm32f103 board

Does my NVIC configuration wrong?

Code:

@ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)

.thumb
.cpu cortex-m3
.syntax unified

.word   0x20005000
.word   start + 1

b   start…

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Code Size – a comprehensive comparison of microMIPS32 and Thumb code size using many Megabytes of customer code

Ian Johnson

In this blog I take a close look at the code size of ARM’s Thumb instruction set against the microMIPS32 instruction set, as used in the microAptiv processor family. More specifically I look at recent claims that microMIPS32 has 17%-30% better code…

over 6 years ago
Processors
Processors blog