Hello all,
I'm new to the ARM platform and I'm having a problem discovering why my code is generating a Hard Fault.
My hardware is an mbed platform board with the NXP LPC1768 processor.
The code in question works when compiled using the mbed…
Hello,
so I was working on Tiva C launch pad and coding using this environment, I noticed that this compiler has major difference from others so I will list some of the problems I faced as questions hoping someone would answer :
1- In case I need to use…
Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…
Hello,
I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.
However…
Where the system designer wants them to be, of course!
There is no restriction on where the various software modules reside. As with all other Cortex-M processors, the system designer is at liberty to build the solution that has the best fit for the target…
Hi,
II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.
D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…
Hi,
I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.
And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…
Hi,
I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.
I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…
eXecute-Only-Memory (XOM) is a firmware protection technique to help prevent 3rd parties from stealing or reverse engineering firmware, and at the same time allowing 3rd parties to add additional software to the…
Overview of stack size requirement estimations in Cortex-M based applications
“How much stack memory do I need for this application?” - This is a common question for many software developers working on applications that run on microcontroller…
I want to use a structure as given below on my ARM Cortex-M0, I am using C programming.
struct path_table_t {
uint8_t lut_index;
uint8_t flag : 1; };
'flag' field is made to be single bit by bit fields.How will be the memory allocation for the array of above…
ARM is introducing a new processor-specific ELF section attribute flag SHF_ARM_PURECODE. This attribute aims to facilitate the separation of instructions and data in program's memory when targeting micro-controllers.
Micro-controllers are important…
