Hard fault in STM32F101RF due to MRC2 Disassembly ??!!

Vish_

Hi all,

I am having a bootloader code wherein I will sending/receiving data via USART . I have configured USART to operate in interrupt mode.

USART functionality works perfectly fine independently. Verified this with multiple read/write instances.

When…

ARM Cortex-M3 floating point...

dtvonly dtvonly

Note: This was originally posted on 9th May 2008 at http://forums.arm.com

Hi. Are there any floating point support for the ARM CORTEX-M3?

Abort some questions of arm interrupt

josh zhao

Note: This was originally posted on 20th June 2008 at http://forums.arm.com

I try to understand arm interrupt,there are some questions I don't know,
1. Why the nested interrupt has to switch out of irq mode to svc mode? I think it only pushes…

ARM9 replacing Cortex M3

Michael von Hauff

Answered

Cortex M3 compilers and benchmarks

Andrey Madan

Note: This was originally posted on 20th January 2009 at http://forums.arm.com

Please help me identify the best compiler for CortexM3.
I currently use armcc from ARM, but curious if that is the best option on the market. So far, I found a couple of options…

Bus Matrix

Felix Varghese

Note: This was originally posted on 28th January 2009 at http://forums.arm.com

What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?

over 6 years ago
System
SoC Design forum

ARM Cortex ICode, DCode, System buses

Felix Varghese

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?

…

over 6 years ago
System
SoC Design forum

Shortest code for memory to memory transfer

subin t

Note: This was originally posted on 16th March 2009 at http://forums.arm.com

Hi All,
Can anyone tell me what is the shortest code I can use for cortex M3 to transfer (a few words) from one memory location to other(without using the DMA). It should…

Invalid assembly instruction MOV PC, R13 Cortex M3

Umut Umut

Note: This was originally posted on 24th March 2009 at http://forums.arm.com

Hi,

I am trying to compile linux kernel 2.27 with CodeSourcery GNU toolchain 4.3.2 and somehow I am getting assembler error for instruction

MOV PC, R13

Well, for some reason ARM…

What is the general purpose register number for LR in Cortex M3

Umut Umut

Note: This was originally posted on 25th March 2009 at http://forums.arm.com

Note: Topic title is not valid. It should be "What is the general purpose register number for FP in Cortex M3"

I would like to know which general purpose register is…

Precise Memory Error

Susan Davies

Note: This was originally posted on 3rd August 2010 at http://forums.arm.com

I am working with a Cortex-m3 using assembler and am getting "precise memory errors". The manuals refer to this fault a lot, but don't actually explain what it IS and how to…

Question : The Definitive Guide to the ARM Cortex-M3

Kenichi Kenichi

Note: This was originally posted on 11th December 2007 at http://forums.arm.com

Dear, all.

I am new in this forum.
Recently I studying Cortex-M3 core, so I bought book "The Definitive Guide to the ARM Cortex-M3" by Joseph Yiu.
This book is very…

[CM3]UART always lose the last char

stupidMokey

Hi,there.

I am using UART of my CM3 board,and there is something strange.

I use minicom(a friendly serial communication program for linux) to Rx data came from CM3,and every thing goes well except that the last char is always lost. I have followed my program…

Answered

Cortex-M3 Hard Fault - find cause?!?!?!?

Tim Borland

Hello all,

I'm new to the ARM platform and I'm having a problem discovering why my code is generating a Hard Fault.

My hardware is an mbed platform board with the NXP LPC1768 processor.

The code in question works when compiled using the mbed…

Answered

I want to know priority of Cortex-M3 processor

kyujin

which interrrupt priority is higher?

systick vs IRQ(external timer)

because In my case externl timer is higher then systick.

I saw that during processing in systick ISR, but suddenly pc jump to timer ISR

so I experimented print out. systick print letter…

Answered

Cortex M3 - Conditions for IT folding

Remi DUCLOS

Hi folks,

Some weeks ago, I discover the mechanism of IT instruction folding supported by the cortex-M3.

As mentionned in 'Cortex-M3 Devices Generic User Guide', "In some situations, the processor can start executing the first instruction in an IT block…

Answered

Cortex-M3: Are "Errata Notice" and "Software developers Errata Notice" the same?

J K

Im wondering if these documents are different types:

1. Errat Notice, PR141-PRDC-007452, v9.0, 2008

2. Software developers Errata Notice, ARM-EPM-039114, v2.0, 2014

From my point of view, these documents are the "same" (of course in another revision).…

Answered

Cortex M3 - Literal-pool vs MOVW-MOVT when cache is present

Remi DUCLOS

This question is a kind of survey:

Hi folks,

I know this subject, or almost the same, has already be presented, but I don't found an appropriate answer.

First, a short reminder

The Cortex-M3 instruction set offers three ways to load a 32-bit literal…

Answered

Yet another processor crash!

Chris Williams

Yes, my ARM cortex M3 is crashing, whats new?

Well, after 3 weeks of debug I am no closer to an answer, so I hope you will not mind if I list what I have tried and see if anybody has a flash of inspiration?

The setup:

Bare bones LPC1788 ARM Cortex…

ARM : LPC2148 Registers and programming examples

Satya Prakash Prasad

I am a beginner in using ARM LPC2148 MCU for project purpose. I searched for details about tutorials, example set, registers details of MCU but could not find much.

Please let me know site that would be useful for me to avail the datasheet, examples and…

Answered

"Dormant Mode" for Cortex M3/M4

Steven Dennis

Hi,

We are interested in minimizing startup time from deep sleep mode.

Some of the older ARM cores implement a dormant mode whereby the CPU core context (state) is written to RAM prior powering it down, and then then restored after the CPU core is powered…

Cortex-M3: What happen to the stack pointer (sp) when setting VTOR?

J K

The first entry of the vector-table is the initial value for the stack-pointer.

I'm asking me, will the stack-pointer be changed when VTOR was set?

Thanks for any help! :-)

Answered

LPC1837 Backup Registers

Jonathan Barnett

The processor has 64 registers (256 bytes) in the RTC power domain

I am using these registers to store temporary data which then gets committed to flash at the end of a transaction.

I can read / write data ok but am getting some odd reads at times.

The Datasheet…

Answered

real time digital signal processing and its performance analysis

Xingjun

Hi, Everyone.

I am working a on project that requires the use of LM3S8962 evaluation board and keil uvision compiler.

I need to program fft in c algorithm and allow my micro-controller board to process it.

I have the fft algorithm. I not too sure my fft…

Answered

Cortex M3 peripheral Bit Banding limit?

H van Rooyen

Is there an intrinsic limit to the width of the bit banding for peripherals for the

Cortex M3?

EFM32 Giant Gecko seems to have a limit of eight bits - bits 8 to 31 does not seem to work.

Is this normal?

Answered