HI,
I am trying out the Cortex M1 on an altera FPGA. I have an example implementation from the Altera kit which uses ITCM to load the software files on the ARM. I want to instead…
am trying to load the ARM Cortex-M1 soft processor on the pynq Z2. I am writing a simple C program to read values from an array and displaying it on the Jupyter notebook. This does not seem to work as when I saw the waveform on Chipscope, the read address…
Hello ARM Community,
some time ago I started with Cortex-M1 core on Actel Proasic3L FPGA. I don't have much experience, but I have development board without working example:) I tried to follow Actel's tutorials and create simple LED blinking application…
I have been spent about 2 months trying to find a faster way of multiplying 2 32-bit numbers giving a 64-bit result. It is truly driving me mad because it FEELS like their is a faster solution. I should add that this example is for a 100% assembly-language…
Dear sirs,
I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.
When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.
(I configure for using Spartan…
Hello all,
I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…
Hi,
I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.
I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…
Hi, My name is Vedula. My back ground is 23 yrs in ASIC industry. Did Design/Verification/Validation. I want to get my hands dirty with DesignStart. I am interested in FPGA part.
I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.
To start with…
Hello,
I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…
Hi.
I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…
Hi I'm very excited to announce of the release of a new product we have been working on for the last few months called the Cortex-M Prototyping System, as part of the Versatile Express family of products. This development board is targeted at the evaluation…