Hi.

Currently. I'm trying to understand about system memory in cortex m3 address map.
most examples are said "there are 2 area such as 0x08000000 Flash memory area and
0x1FFFF000 System memory area.

and I understood that Flash memory area is saving…

Dear All,

I came across initial function as the below,

void UartStdOutInit(void)
{
CMSDK_UART2->BAUDDIV = 16;
CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only
CMSDK_GPIO1->ALTFUNCSET = (1<<5);
return;

}

At the first time this function…

Hi.

As I know Cortex M3 design kit have lots of  stuff IP. one of those things is cmsdk_ahb_busmatrix.

But I want to know does cmsdk_ahb_busmatrix supports AHB-full specification? or just supports AHB-LITE?

I'm confuse that because there some example explained…

Dear All,

Now I'm trying to digging the M3 operation in especially reset sequence with hello example of cortex design kit.

Current situation is that reg14[31:0] is fixed in 0xFFFFFFFF and reg15[31:2] is 0xXXXXXXXX unkown value. the other regs are…

Hi Now I'm trying to digging the design kit.

But I cant' find the BOOT relative port or signal and REMAP signal in the design kit.

As I know usually BOOT used such as the following picture

But I can't find any relative interface in the design…

Hello?

I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM  in Keil MDK.

As you can see the above example system, AHB Interconnect have 3 slaves S0, S1 and S2. and S0 and S1 are connected with…

• Dear all,  

I believe that you know such as STM32F103 cpu series support firmware program function by using JTAG with JTAG debugger of keil MDK.

So I want to know does cortexm3 design kit include such as  JTAG firmware program function blocks? 

What am…

Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more…

Hi everyone,

I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins…

Hi.

TESTNAME=bootloader test sequence is in  BP210 CM3 test sequence,

In especially, we could find the below code,

then we got the below error message when we ran the simulation.

23490 ns UART: CMSDK Boot Loader 
27270 ns UART: - load flash 
45710…