As a product manager for the Cortex-M33, I see this question pop up a lot. Below is my version of the answer.

Characteristics of TrustZone technology

• TrustZone is the security foundation for billions of ARM Cortex-A processor-based systems
• TrustZone…

Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…

This is a very common question.

The diagram below is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

• Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…

This is a very common question too.

The diagram is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

-Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

-Using the same debug…

Hello,

I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

However…

What is the difference between the TrustZone of Cortex M23/33 and the TrustZone of Cortex A?
Can you provide documentation on this topic? May I start to prototype my Cortex M23 application on a Cortex A processor and then migrate to Cortex M23 when chips…

Hi,

In RTOS Design Considerations Version 2.0 document, Section 2.2 ("SVCall and PendSV exceptions") following is mentioned.

When the processor is in Secure state, the SVC exception handling sequence fetches the exception vector from the Secure…

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

Hi.

How do I start with simple example for study about boot rom and boot sequence?

I'd like to make a simple architecture, but first of all, I have to make a L1 boot and L2 Boot code as I know.

CM3 is connected with boot ROM and Flash.

So Would you…

All,

I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

I saw, and tried in the past already, to simulate the Cortex-M0. It does not really matter efficiency, customization and so on, but only the learning process behind a steup for a correct very basic simulation.

I was trying to setup a Linux machine, when…

Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…