Hi,

I find C code not executing in the desired way. Then I step in assembly code of Tiva-C M4F core. Below is the disassembly code:

$C$L5:   nop

0000033a:   280A     CMP             R0, #10…

According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

"Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…

Hi all,

I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).

There are several ressources available…

Dear sirs,

Regarding v7m debug architecture, I have some questions after reading the v7m architecture document.

Q1: There is no mechanism to send instruction to the core for execution in debug state, is that true?

I guess the architecture uses  debug return…

Hello guys,

I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.

Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?

Thank you very much.

Hello All,

Good Morning!

I am working on Cortex m4.

I have read following about hard fault ,

"Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.

The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

The ICI bits at the time of the interrupt equal 7. This means that…

Hi,

I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…

I want to communicate NXP LPC2378 (ARM7 core) to some other devices via SPI (Serial Peripheral Interface) protocol.

So how to write a C code to communicate a particular device as a Slave with Master (ARM7 controller)?

I believe that many of us are interested in the ARM Cortex-M7.

Recently, jyiu posted a status update, where I asked a couple of questions about the architecture.

A few questions on the subject was also asked in the Interview and Question Time with Joseph…

I need some indications to begin writing a program.

Write a compare routine to compare 64-bits values , using only two instructions.

Thanks for your indications !

Hi,   I am new to ARMv8 architecture and while reading the v8 exception vectors I am not able to understand significance of adding SP_EL0 level vectors while SP_ELx vector set exists. What I am trying to find a use case where this is useful. I understand…

what are the minimum hardware requirements to setup wifi on arm-7 processors.

Greetings,

               Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg

niallcooling's Developing a Generic Hard Fault handler for Armv7-M

also:

http://supp.iar.com/Support/?Note=23721

https://community.freescale.com/thread/306244 - which…