Hello:

I need more  RAM size on MSP2 board.

in Keil  uVison 5, I add a simple code to write then read testing.

//-------------------------------------------------------

ram_addr=(volatile uint32_t *)(0x20400000);

for (j=0; j<1024; j++)
{
*ram_addr…

This is an update to the fimware for the MCC on the MPS2+ board. This adds some features for improved compatibility with the Mbed OS software examples and continuous integration flow. You do not need to install the update unless you are working with Mbed…

Hi there,

Why the address of reset handler is different from waveform and assembly code for hello testcase?

This is obtained after compiling hello.c using Keil uVision 5.

Reset_Handler
0x000001c0: 4809 .H LDR r0,[pc,#36] ; [0x1e8] = 0x2a1
0x000001c2:…

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Cannot configure interupts of TIM6 on stm32f103 board

Does my NVIC configuration wrong?

Code:

@ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)

.thumb
.cpu cortex-m3
.syntax unified

.word   0x20005000
.word   start + 1

b   start…