Hello,

As part of my diagnostic regime I wanted the diag to halt when completed.  It doesn't seem like it can.  It seems to keep running when I 

  CoreDebug->DHCSR = (0xA05FUL << CoreDebug_DHCSR_DBGKEY_Pos) |
                     CoreDebug_DHCSR_C_HALT_Msk…

Hello to all,

Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

Is the processor also use the method of "Forwarding" in order to handle…

Hi 

Now I'm trying to understand about memories in the Cortex design kit.

I came across memory address map of cortex M3 when I googling as the below.

In the image, left one is an AHB memory map, and right one is STM32F103's memory map.

As you…

AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…

This is a very common question.

The diagram below is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

• Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…

This is a very common question too.

The diagram is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

-Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

-Using the same debug…

Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

Hi,

I am trying to get familiarize with the SoC design provided with Desgin Start Cortex-M0 Eval version.

Here is my setup:

1. ARM Cortex-M0 core
2. Design Start Eval  with CMSDK used for SOC design.
3. Keil MDK – mdk_pro uvision V5.25.2.0
4. Vivado Tool used…