Root of Trust implementation – Connected devices with authentication requirements need a root of trust in the system architecture. This is particularly important for devices that can be updated over the air. In a system with TrustZone technology, code…

This is a very common question.

The diagram below is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

• Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5…

This is a very common question too.

The diagram is a pictorial description of the differences followed by some explanations.

Starting from the bottom:

-Cortex-M23 is an implementation of the ARMv8-M architecture. Full details here.

-Using the same debug…

Hello,

I am using Cortex-M33 FVP model to run the Keil RTX TrustZoneV8M RTOS example.
Have also tried to experiment with the memory map configuration and the corresponding SAU region programming for NS/S patitioning and the behaviour is as expected.

However…

Hi,

I'm starting to explore this technology by running the TrustZone example application in Linux using GNU ARM Toolchain. This example is provided by a CMSIS software pack containing this example called "TrustZone for ARMv8-M No RTOS" which I was…

Where the system designer wants them to be, of course!

There is no restriction on where the various software modules reside. As with all other Cortex-M processors, the system designer is at liberty to build the solution that has the best fit for the target…

Why should we call secure function in handler mode? What is the design purpose for this?  As we know, none-secure side can also call secure function in thread mode.

I have a set of tasks in FreeRTOS and I need to put some of them in the secure world (Trustzone).

Is there a communication to be established between the SMC trustZone side and the scheduler FreeRTOS side ?

tracks please.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

Hi.

I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.

there is some options in makefile such as 

# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…

Hi,

I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

Critical…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

But, unfortunately after compiling the RTL I am getting a stack…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

to compile the RTL and run the tests.

But, unfortunately after compiling the…

Hello,

For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

If I try to compile the ".sof" file of the Eval package in Quartus Prime…

Hi,guys.

We have already  applied for Cortex-M3 DesignStart Pro and purchased the V2M-MPS2+ motherboards.

To my knowledge, V2M-MPS2+ motherboards was designed for DesighStart Eval and can be integrated with arm Embed OS easily.

So, my question is:

1, can…

Hello,

I'm trying to connect the DesignStart Eval System to the BME280 Environmental Sensor via SPI. I used the SPI Shield0 Pins (EXP[11 to 14]) to set the connection and activated alternate functions in uVision for these pins. But how can I set up the…

Deare

       I am using Cortex-M0 DesignStart Pro. When I use my program to simulation, I found the HADDR from 0, to 4, and the to ffff_fffd8, the  HRDATA is  0x2000_06f8 and 0x800_0159，the HADDR should not be ffff_ffd8，So I think it's unusual, but I don't know…

We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…