• DMA Failing on Vision Application using Cortex-A9

    Adam Garrison
    Adam Garrison

    Camera Interface DMA goes bonkers and we need a work around or understanding of how this can happen so we can stop it.

    We currently are running the IMX6 SL @ 792MHz with X16 DDR3L @396MHz. Core voltage is 1.375V

    we are finding that the CSI peripheral gets…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PL310 cache synchronization

    Vincent Siles
    Vincent Siles

    Hi !

    I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.

    - when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0

    …
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 single core

    Vincent Siles
    Vincent Siles

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use the amba bus?

    Idan
    Idan

    Hello,

    i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

    i have searched a lot but I probaly miss the point.

    i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding mismatched memory attributes and cacheability

    Hemant
    Hemant

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU?

    hello_arm
    hello_arm

    Can anyone help?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why A9 is multicore by A8 doesn't

    techguyz
    techguyz

    Hi Experts,

    Which factor in processor decides whether it can be used in multi-core or not ?

    Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACTLR[1] question in Cortex-A serias SOC

    chinatiger
    chinatiger

    hi, experts:

    I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

    I have some questions about out cache concept in Cortex-A7.
    1. Some program disable outer cache by setting ACTLR[1] = 0.

       So, is it only available with Cortex-A9…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Basic cortex A9 architecture question (memory area division)

    Senthil Kumar Rajagopal
    Senthil Kumar Rajagopal

    Hello all,

    I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .

    The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.

    On Reset, the CPU 0…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • D-side prefetch Cortex-A8

    Andreas Hauser
    Andreas Hauser

    Hi at all!

    At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4.

    Now I'm a little bit confused about the handling for enabling…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9 core registers

    Jay Zhao
    Jay Zhao

    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.

    So how can I match them with R0-R14, especially…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Supported AXI transfers on Cortex-A9?

    Martin Trummer
    Martin Trummer

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • share memory between core0 (linux) and core1 (bare-metal)

    Mike
    Mike

    Hello,

    i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

    Thanks,

    Mike

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • code compile using -mcpu for ARM platform

    Jay Zhao
    Jay Zhao

    When using gcc to compile c code for ARM platform, we set object platform by using:

         -mcpu = xxxxxx

    To what extent will that affect results of compiling ?

    For example:

         -mcpu = cortex-a8

    and

         -mcpu = cortex…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • General Feature of Cortex processors on cache coherency

    techguyz
    techguyz

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The merit of data cache cleaning

    Henry Choi
    Henry Choi

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to run an ARM 32bit binary on Juno Board in Linux and Android ?

    zzliu
    zzliu

    hi, guys:

    Currently, i want to execute a Cotex-A9 binary compiled by ARMCC on Juno board(OS is linux).

    But when i ran it, it reported that "XX: No such file or directory".

    My questions are:

    (1) Did somebody meet this problem before ?

          and could…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9/GIC: de-activate an active interrupt

    42Bastian
    42Bastian

    Hi

    my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

    No the problem: If the normal-world error happens in an…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

    anoop
    anoop

    i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

    when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

    but there are some printing commands that prints variables used, when i disable them i got…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • does different arm TRM revisions also have changes in Hardware?

    anoop
    anoop

    Hi

    I have an inquiry. our company is using Cortex-A9 quad Core. So in ARM website there are many technical reference manuals for the same in different revisions , such as:

    r2p0

    r2p2

    r3p0

    r4p0

    r4p1

    so what should i follow?

    or should i follow latest revision?

    or…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 - GICv4 Documentation

    anoop
    anoop

    i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • question about arm cortex-a9 neon optimization(4x4 matrix mul)

    Jin, Soonjong
    Jin, Soonjong

    =======================================

    for matrix 4 by 4 multiplication, neon programming is slower than natural code with

    auto-vectorization option. (Xilinx Zynq 702 EVM board - cortex a9 with gcc complier option

    -mfloat-abi=softfp -mfpu=neon-fp16 -ftree…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Questions about Generic Timer in ARMv8

    wangchj
    wangchj

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore

    Niranjan Dighe
    Niranjan Dighe

    Hello all,

    I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register

    readable and writable by the following instructions -

    MRC p15,0,<Rt>,c5,c1,0

    MRC p15,0,<Rt…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Software Radio Based on ZedBoard and AD-FMCOMMS1-EBZ

    hgli
    hgli

    ARM friends,

    I have done some research on software radio based on ZedBoard and AD-FMCOMMS1-EBZ.

    ZedBoard is a development board which uses Xilinx Soc FPGA.

    Xilinx Soc FPGA includes ARM Cortex A9 dual-core and Xilinx FPGA.

    ZedBoard runs Ubuntu Linux operating…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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