• 使用Streamline分析RTOS系统性能

    章政
    章政

    本文翻译自Analyzing the performance of RTOS-based systems using Streamline

    =============================================================

    Streamline是DS-5中的性能分析工具, Streamline可以用来分析裸机系统,RTOS,Linux,Android和Tizen系统的性能。

    通过Streamline可以更详细地了解软件的运行,让arm优化工作更简单,你可以将游戏运行的更流畅…

    • over 2 years ago
    • 中文社区
    • 中文社区博客
  • Analyzing the performance of RTOS-based systems using Streamline

    Stephen Theobald
    Stephen Theobald

    Streamline is a Performance Analysis tool that comes with Arm's DS-5 Development Studio (DS-5). Streamline enables you to analyze the performance of bare-metal systems, systems with a Real Time Operating System (RTOS), as well as systems based on…

    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • DS-5 Bare-metal code - Accessing my host NIC card drivers

    Ab
    Ab

    Hi there, 

    Is there any way from DS-5 development studio to access my host NIC ethernet card? 

    I want to write a bare metal code (Cortext A9),  creating an ARP packet on DS-5 and I would like to test it if its working with my host NIC Card drivers. 

    Is it…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Load / Store timings with different cache settings

    superdesk
    superdesk

    Hello,

    I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program on a single core of a Cortex-A9 on a Xilinix Zynq-7000…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Migrate to Arm Compiler 6 from gcc

    Ronan Synnott
    Ronan Synnott

    In a previous article I wrote about migration from armasm (the legacy Arm assembler) to Arm Compiler 6 (AC6). This was useful for users who were already using the Arm toolchains for their builds. But what of gcc users?

    Previously there was a reasonably…

    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Nutsboard Cortex-A9 SoC开发板活动结果发布

    Song Bin 宋斌
    Song Bin 宋斌

    各位用户大家好,

    谢谢大家的积极参与,截止今天中午12:00,此次一共有22位朋友参加,我们正在请Nutsboard的Wig兄帮忙审核,并确定获奖名单。

    先公布一下选择题的答案

    1)a

    2)c

    3)d

    4)b

    5)c

    以下是Wig兄给大家打的评语,后面显示结果是pass的就是能获得开发板的用户,后补1,2,3...是表示如果前面10位有人放弃或者不要的,我们将按照顺序后延。每位pass获得开发板的用户,请在下周五, 10月20日中午12:00前,发送你的快递方式到我的邮箱ben.song@arm…

    • over 3 years ago
    • 中文社区
    • 中文社区博客
  • A9 Code after vector table

    josecm
    josecm

    I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disabling L2 cache for CPU1 (Zynq-7000)

    irie
    irie

    Hello people,

    we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one handles DMA configurations and its interrupts. We have…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMP system on Cortex-A9. How to do it?

    pinchazer
    pinchazer

    Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…

    • over 3 years ago
    • System
    • SoC Design forum
  • ARM Cortex-A9 Preload and Lock Code in L2C-310

    josecm
    josecm

    I've been studying and experimenting with the caches on an ARM Cortex-A9, namely a Zynq SoC, for the past week with the main objective of loading and locking part of my code to L2 (PL310). The steps I take to achieve this are:

    • Set TTBR0 and Invalidate…
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • 社区用户何老师精心制作视频课程

    Song Bin 宋斌
    Song Bin 宋斌

    大家好,

    很多朋友可能知道,我们ARM社区用户藏龙卧虎,各有各的高招。他们自己还有很多宝贵的资源,可以分享给其他用户。

    今天,我推荐一下社区用户何老师的视频课程。

    何老师(何宾)是一位北京的大学教师,对于处理器,FPGA和电子科学非常了解,熟悉,他自己也为学生上课,业余时间编写ARM相关教材,在行业内很有知名度。

    最近,何老师告诉我们他分享了他的课程视频,给大家免费观看。

    希望对大家学习ARM有一定的帮助。

    以下是课程链接:

    http://edawiki.com/

    此课程适合学习Cortex-M0处理器…

    • http://edawiki.com/
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    • over 3 years ago
    • 中文社区
    • 中文社区博客
  • 想嘗試新的工控開源解決方案嗎

    NutsBoard
    NutsBoard

    我們是NutsBoard,是一個新的工控解決方案平台,主要是以核心板與單板電腦的形式先向我們購買您有興趣的標準板,若有興趣客製化也可以再與我們討論後續事宜,所有軟體皆為開源,支持多種操作系統,所用的平台以NXP與TI為主,有興趣的人可以聯絡我或是到網站參觀喔,希望可以幫助到ARM平台在工控領域的人們!

    mail: onlywig@gmail.com

    website: http://www.nutsboard.org

    • over 3 years ago
    • Arm mbed 中文技术讨论区
    • Arm mbed 中文技术讨论区
  • Porting code From Cortex-A9 to Cortex-R7

    Ajeesh
    Ajeesh

    Hi,

     

    I have some bare metal code written for Arm cortex A9. I would like to port this code to cortex R7. Since both of them belong to ARMv7, How much effort will this take?

    I have never worked on cortex R processors. Will i be able to use the same assembly…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Processor Modes in cortex-A57

    Ajeesh
    Ajeesh

    Hi,

    I have done some basic assembly in Armv7-A processors (cortex A9). The version of ARM supports modes like User, sys, SVC etc. Does the ARMv8 also has the similar modes? Where can i find the details. Please point me to the documents if any.

    Regards…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Porting code from Cortex-A9 to Cortex-A57

    Ajeesh
    Ajeesh

    Hi,

    I have been using I.MX6Q Sabre sd board (cortex-a9 ). I build image with my own start script and ld script. The image was loaded with u-boot. Now i would like to do the Same with Renesas R-Car M3(cortex A-57). How would i go about this? Can i use the…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible at all to inspect DCACHE line bytes (and flags) on the Cortex-A9 core by reading/writing CP14 or (less likely CP15)?

    Lukasz
    Lukasz

    I'm trying to fix problems related to Dcache enabling on Cortex-A9 based board.

    Is it possible to inspect cache line data? How I should do it? Shall I use CP14?

    I do know that with Lauterbach's TRACE32 it was possible to modify and inspect cache content…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 single core

    Vincent Siles
    Vincent Siles

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

    Abhilash VR
    Abhilash VR

    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.

    From JTAG, Read works properly but writes makes the specific cache line corrupted,

    Step 1 : Initial Setup

         1. Wrote an application Which runs from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 second execution unit

    Kushal
    Kushal

    Dear All,

    I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU).

    Till now i was able to find quite limited references that were not much helpful.

    If any…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Need to invalidate L1 cache after DMA on Cortex A9

    Rohan
    Rohan

    Hi,

    I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Periodic activities in the systems when the idle state is dominant

    Mohamad Ahmad
    Mohamad Ahmad

    hello everyone,

    I am working on the systems in order to observe their behaviour on the DS5. I execute the system by an application benchmark and I watch the behavior of the DS5 Streamline data. when I have treated the data of execution I have a part where…

    • over 4 years ago
    • Software Tools
    • Arm Development Studio forum
  • BDI2000 调试器 无法 halt cortex a9 核心(linux 系统异常时)

    yuanlinyu
    yuanlinyu

    hi,各位arm专家,
    我最近有个arm linux平台项目,使用的是mindspeed 公司 的m85374, 双核arm cortex a9。

    遇到一个问题, linux内核启动后,执行init 脚本阶段, 系统偶尔死掉。

    用BDI2000调试器定位问题的时候,出现无法halt cpu的情况,

    csp@1>halt
        Core number       : 1
        Core state       …

    • Answered
    • over 5 years ago
    • 中文社区
    • 中文社区论区
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