• A question aboout Monitor Vector Base Address Register(MVBAR)

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore CPU, It supports the trustzone tech.

    I tried to switch the non-secure world to secure world in Linux but It is hard to implement.

    I have a question about the trustzone about Monitor Vector Base Address…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API

    eli.z
    eli.z

    Hi,

    In my system (CycloneV - 2 cores of Cortex-A9) I require large DMA transfers, and currently I can't connect DMA via ACP, so cache coherency becomes SW problem. I know that the proper way of doing it under Linux is using the DMA-MAPPING API, and…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Compute Library in Xilinx SDK for bare metal execution?

    Anto85
    Anto85

    Hi all, 

    I'm trying to add the ARM compute library on Xiling SDK to run a CNN on the Cortex A-9. I'm having a hard time trying to integrate it. To begin with, i downloaded the ComputeLibrary master folder at https://github.com/ARM-software/Comp…

    • over 1 year ago
    • Open Source Software and Platforms
    • Machine Learning forum
  • Why NSCAR(Non-secure Access Control Register) changes often?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore CPU, It supports trustzone tech.

    I tried to change NSACR.TL bit, but It needs to change in the secure state.

    I checked NSACR value in non-secure state and NSACR value that I changed is changed aperiodically…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Autodetection failure when trying to debug a bare metal platform with ARM development studio and dstream

    SRK
    SRK

    I have an ARM cortex-A9 based bare metal platform that I am trying to debug with dstream and evaluation version of ARM development studio (installed on a windows 64 bit machine)

    I tried adding/detecting the platform via auto detection (File->New->hardware…

    • over 1 year ago
    • Software Tools
    • Arm Development Studio forum
  • How to use Secure Monitor Call(SMC) and entrance Monitor Mode?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore cpu, It supports trustzone tech.

    I want to change NSACR.TL bit, but It need in secure state.

    I want to change non-secure state to secure state by entering monitor mode using smc.

    But It is not easy to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • dump MMU translation table for A9 in Linux

    mivascu
    mivascu

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to check PTM trace from the ETB without using JTAG or other adaptor

    G1_Chang
    G1_Chang
    Hello. 
    Im using I.MX6 solox Board from NXP Cooperation.

    This I.MX6 solox has a Arm Cortex-A9 processor.

    What I am trying to do is Tracing PTM which will be stacked up in the ETB buffer. 

    I also used Zynq 7000 zc706 which has two Arm Cortex-A9 processors…
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU initialization for an ARM multicore system

    ddn
    ddn

    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

    On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How can I use imx6 in Asymmetric (***) mode?

    MARCO MANTOVANI
    MARCO MANTOVANI

    I would like to use iMX6 in asymmetric mode (Windows EC7 + Linux). Is that anyhow possible? Marco

    • over 7 years ago
    • System
    • Embedded forum
  • Cortex A9 dual core - How to achieve an AMP system without an RTOS?

    Senthil Kumar Rajagopal
    Senthil Kumar Rajagopal

    One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end

    image analysis task). Due to cost or other over head reasons, he/she does not prefer to use an RTOS…

    • over 7 years ago
    • System
    • Embedded forum
  • TCP/IP stack for Cortex-A9 MPCore

    Jacques Perti
    Jacques Perti

    Hi,

    I'm currently working on a project based on the Arria V SoC FPGA (ARM Cortex-A9 MPCore). The goal of this project is to run a high speed ethernet link.

    For some reasons the customer don't want to use a Linux kernel on the ARM. His wish is to have…

    • Answered
    • over 6 years ago
    • System
    • Embedded forum
  • Anyone knows of any Cortex-A9 development boards?

    Chin Beckmann
    Chin Beckmann

    We've been using TI's Panda board but it seems to give us quite a bit of trouble.  As a result we can't profile the information that we would like.  Does anyone know of any other development boards out there that has a Cortex-A9 on it?  And what experiences…

    • over 7 years ago
    • System
    • Embedded forum
  • ARM Linux: Can I control cache flush and invalidation in user space?

    Cyberman Wu
    Cyberman Wu

    These days I'm using Xilinx SoC to design a software, which shares memory between Cortex-A cores and FPGA.

    I've tried reserve memory in Linux and mmap() /dev/mem. The problem is if I use O_SYNC, it very slow since

    my software access every byte computed…

    • over 6 years ago
    • System
    • Embedded forum
  • L1 Cache Eviction Corrupting DDR on A9

    yottaflop
    yottaflop

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • How to configure Interrupt vector table ?

    Ajeesh
    Ajeesh

    Hi,
    I am using I.MX6Q Sabre sd board (cortex-a9 ). I am trying to build custom image with my own start script and ld script. The image is to be loaded with u-boot. Where should i place the Interrupt vector table? Now, when i reffered the "1.1.0_iMX6_Platform_SDK…

    • Answered
    • 10800.zip
    • over 4 years ago
    • System
    • Embedded forum
  • Converting virtual address of Instruction fault address register to physical address in cotex A9

    Abhishek kumar dubey
    Abhishek kumar dubey

    Content of IFAR=0xaa4e8ef0

    IFSR=0x0000000d

    DFSR:0x00000000

    DFAR:0x00004000

     

    How to find Physical address form this?

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • Interrupt status in Aarch64

    uditknit
    uditknit

    Hello, 

    In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]

    I am looking for if there is similar register present in A64 architecture . 

    Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or…

    • over 3 years ago
    • System
    • Embedded forum
  • How to read ARM A9 registers in C?

    Helena
    Helena

    Hello!

    I'm using a Zybo board with a dual-core ARM Cortex-A9 processor and I'm trying to read (and then write) the registers of the processor. How can I read these values into variables in C code?

     

    Thank you!

    • over 2 years ago
    • System
    • Embedded forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Yeli
    Yeli

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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