Hello ;
I am working on Arm Cortex-A53 and here is the problem;
when ı am trying to allocate
A= new comp[N]; >>
typedef std::complex< double > comp;>>
#include <complex>
struct complex<double>
{
typedef double value_typ…
Hello ;
I am working on Arm Cortex-A53 and here is the problem;
when ı am trying to allocate
A= new comp[N]; >>
typedef std::complex< double > comp;>>
#include <complex>
struct complex<double>
{
typedef double value_typ…
Hello everyone,
I am having difficulties on compiling Ne10 library with ArmCompiler 5. As I understand, Ne10 library requries a GNU compiler, or ArmCompiler 6 which is more GNU like, however currently we are using ARM Compiler 5 in our project.
Is there…
Hello everyone,
In the project I am working, I am running a Real Time Kernel on the Primary Core(uCoS-III) and use Secondary Core as BareMetal for Algorithm Execution and delegate algorithm execution job to the second core with software generated interrupts…
Hello guys,
I've been running the same code (that you can find here https://gist.github.com/poz1/1714ddd68da5816624d6867ad6cc5d98 ) on an R5 Board and an A9 Board.
Optimisations are enabled and my goal was to find the "right clock" for the A9 in order…
Is it possible to use HW tracing from software?
Means enable trace and read the contents of the ETB from the code running on the same core.
Cheers
Hi,
I am working on some research project based on ZC706 board that contain Zynq-7000 soc. i need to know that is Cortex-A9 Cpu in Zync-7000 implemented Return Stack Buffer (Return Stack Buffer is an program flow speculation technique like branch prediction…
Hello!
The SDRAM starting and ending address in the MPU Address space is modifiable. The window can be enlarged or shrinked at the cost of BOOT ROM region and FPGA slaves region. It is written in TR-Manual that the total amount of SDRAM addressable from…
Hi,
I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…
如题,在四核的Arm Cortex-A9中如何测量Core对共享内存访问的开销?最大和最小开销是多少?这里开销具体是指什么?
需要考虑L1 L2 Cache么?最大开销是不是访问主存(不经过Cache)?最小开销是不是从L1 Cache读写?这里需不需要考虑数据量大小?比如对某块内存memset()写一定大小的数据 几K的。。。其最大和最小开销如何测量?
Arm offers 2 different GCC toolchains: one for Cortex-M/R devices and the other one for Cortex-A devices. However, in the Cortex-M/R toolchain documentation, it is specified that Cortex-A targets are accepted too, so this confuses me: why is there another…
Hi everyone! Please help me.. i have a project with a custom axi slave design that implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…
Is it possible and if so how can i build my own raspberry pi alike?
Can I use this AM4378 | AM437x | ARM Cortex-A9 | Description & parametrics ???
Hi everybody!!
I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).
In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…
Hi,
I have strange symptom with Cortex-A15 device.
The below is traced data.
Program AddressDisassembly
0x40401AA0CMP R12, R0
0x40401AA4BHI 0x40401A80…
Hello all,
do any of the faster application processors (Cortex-A9 and up) have data trace capabilities enabled in their on-chip debug logic? I have been looking at both Xilinx and Altera Cortex-A9 cores, and both of them appear to only provide instruction…
Hi, expert. I'm making CacheFlush function by Virtual Address.
I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9
I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself…
I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.
Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before).
From what I gathered from the documentation of the TZASC and from the…
Hello all,
I wrote end embedded assembly function for an ARM Cortex A9 (the specific device is Zynq, from Xilinx) as follow
float my_fun(float x)
{
asm volatile ("vdup.f32 d0, r0 \n\t");…
For a TrustZone enabled processor, what if a normal world application (e.g. 3rd party application) directly uses SMC instruction to request a secure world entry? In a typical case, it it a responsibility of monitor SW or Secure OS kernel to authenticate…
Hi,
I am programming raspbery pi model b ARM1176 bare metal (in assembly and c). I need to calculate the clock cycles used to execute an assembly code.
I am using the following code for PMU counter:
Hi,
I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.
I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.
SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.
The DMA transfer goes from…
HI,why the VFP vector mode can not be used in cortex-a series processors?