Hello,
i want to use the arm cortex a9 to share memory between both cores. are there any examples online?
Thanks,
Mike
Hello,
i want to use the arm cortex a9 to share memory between both cores. are there any examples online?
Thanks,
Mike
In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.
So how can I match them with R0-R14, especially…
I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…
On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?
Hi Experts,
A8 is meant for single core and A9 is for multi-core based.
Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?
On Cortex-A9, after power on reset BootROM code is executed and this is responsible for configuration of boot media, copy first stage boot loader to on chip memory etc....
I would like to understand the BootROM code flow using step by step procedure(to…
The processor is Samsung's Exynos 4210, ARM Cortex-A9, I want to know whether it supports the L2 cache refill or memory access event?
Hi,
I have seen the ARM webpage for OpenCL SDK for NEON and Cortex-A9.
But I couldn't find any page to download the SDK and test that on Cortex-A9 available in Xilinx Zynq.
Is this SDK available for download?
Thanks
Mohammad
Dear all,
I'm planning to perform a basic embedded augmented reality environment by using codesign "coupling MALI GPU (HW) to ARM processor(SW)".
Please, is there any suggestion for a design platform, for example does DS-5 allow…
Hello everbody,
as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.
Our…
Hello, ARMer,
I am following Mr. Theobald's blog: UEFI Debug Made Easy to run an UEFI BIOS on a FVP of ArmVExpress-RTSM-A9x4. But when building, an error is always reported as below:
17:42:45 **** Incremental Build of configuration Default for project…
Hello,
i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..
i have searched a lot but I probaly miss the point.
i want to use data and to transfer data from the processing system to the programable logic section via the amba bus…
Description of the register architecture (preferably with pictures), including names, sizes and intended uses of all registers
Description of all instruction formats
Description of all addressing modes
THANKS
Hello,
Consider following scenario:
As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ
My question is specific to the case when it is only the cacheability…
Hi,
We found the following document on Cortex-A9 performance.
List of ARM microarchitectures - Wikipedia, the free encyclopedia
Which claims 2.5 DMIPS/MHz per core for Cortex-A9 2GHz@2 core. However, our Dhrystone result on Cortex-A9 1.2GHz@2 core only showed…
Hello,
I have downloaded and installed DS-5 v5.19.1 professional 64 bit on Ubuntu 12.04 (amd64) today. I also applied for an evaluation license, and tried to build the example "startup cortex-A9" project, but I got an error message "C9932E: Cannot…
Hello,
in the DS-5 I have some pre installed FVP (e.g. VE_Cortex_A9x4). I understood these FVP are somehow related to a Virtual Express hardware platform. But I don't understand where do I get the configuration information of the FVP? E.g. if I have a…
Hi,
I am building a cycle accurate simulator for the Cortex-A9 core, and so far I constructed most of the stages of the pipeline.
However I am having trouble placing something that is not clear in any source I have found.
Most diagrams show the prefetch…
In the DS-5 Streamline (Professional 5.19.0) how can I change the "counter" that was used to calculate the number of samples (column Self) in the Functions/Code view?
Consider the scenario where I've profiled an application using several counters…
Hello.
I'm using streamline to profile an application but I'm interested only in the grand finale total sum of a particular counter. Is there this functionality in streamline or do I've to process the whole streamline report output and sum up the values…
Hello.
Is it possible, in ARM Streamline command line interface, to automatically start/stop the profiling session based on start/end of an specific program?
The context is like this. I need to profile different versions of a program (compiled with different…
I am using dual-core Cortex-A9 in a project where 1 core is enough.
How to switch off another unused core?
Hello,
I have a custom ARM Cortex-A9 board. My aim is to load the kernel image onto the target via ARM DSTREAM. I have u-boot loaded into SNOR memory. The u-boot is running fine. After I get the u-boot prompt…
Hello Friends,
I have bought Allied-vision GC2450 GigE camera and download its sample Code for Viewing its Imageries/Video. i need to just compile these sample code by typing command like
# make sample it generate a executable file and
# ./SampleViewer…