• Different performance in HYP and SVC mode ARMv7A?

    ivanpavic
    ivanpavic

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone FIQ latency measurement When security extension is enabled

    Ashwin
    Ashwin

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Quad-Core Cortex A7 / MSDOS comparability

    Scottie
    Scottie

    I just bought a Samsung SM-T560 (WiFi) SM-T561 (3G & WiFi) with a 1.3GHz: Quad-Core Cortex A7. I know nothing about processors but in searching the Internet I have found some applications that will allow Windows OS to run an Android system.

    Is the 

    …
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM PMU access DRAM Event

    pa007
    pa007

    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf

    pagina 243, what event number i neet to select to count all the DRAM access (read / write)?

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Juno r2 L2 and TLB cache

    xpo
    xpo

    Hey guys,

    I need your help because I have to count the number of L2 instruction access, miss and hits. But in the data-sheet I did not find the events that I have to count.

    I found it in the ARM V8 data-sheet. Therefore, is it usable on A72 & A53 even…

    • Answered
    • over 3 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Enabling MMU crashes ARM Cortex A7

    VISA
    VISA

    I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7.

    But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then if i enable the MMU bit from system control register…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • GICv2 initialization for Non-Secure World

    Zizhu
    Zizhu

    Hi,

    Recently I am working on porting our Cortex A7 code that used to run in secure world to non-secure world for some reason. I got a problem when it came to GIC initialization.

    I noticed that in order to manipulate a certain interrupt settings in non-secure…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Inexplicable performance on big.LITTLE technology (on Android)

    Arundale Ramanathan
    Arundale Ramanathan

    I apologise for the long question, but I am trying to measure performance of different indexing techniques on various platforms, one of which is Adaptive Radix tree.

    I have run tests where the basic steps look like this (c/c++):

    Step 1: Generate or load…
    • over 2 years ago
    • Open Source Software and Platforms
    • Android forum
  • Does the DVFS of mali400mp make sense?

    SunnyBeike
    SunnyBeike

    Hi


    Does the DVFS of mali400mp make sense?

    My platform is ODROID, which equipped with the mali400mp GPU.

    I tried to find out how the GPU affect the power consumption of the platform.

    The CPU frequency and bus frequency were all fixed.

    The mali400mp GPU…

    • over 6 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Rescaling the Mali-400

    Keith Manns
    Keith Manns

    Hello, newbie right down to the socks here, but have to ask. From what I've seen most arm cpu/gpu are scaled to to what number of GPU it will use.  I have a Allwinner A31S processor on a device that I know that should be Mali 400 MP4, but it…

    • Answered
    • over 6 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Mali GPU Reading from CPU cache

    maasa
    maasa

    Hi Peter Harris

    In Samsung Exynos 5422, it is mentioned that Mali T-628 GPU is I/O coherent with A15 and A7 CPU and GPU can access data from CPUs cache

    I want to measure the time it takes for the Mali GPU to read from the CPUs cache (A15 or A7). Can…

    • over 3 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • DMIPS calculation for application software on ARM Cortex A7

    Sanjeev Kumar
    Sanjeev Kumar

    Hi There,

    Having below queries : 

    1. We have developed communication protocol stack and ported it on
    ARM Cortex A7 processor. We wanted to know, how to calculate DMIPS for our software.

    2. What is the maximum DIMPS available on ARM Cortex A7?

    Thanks…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Square root calculation results. FPU logic of A15 and A7 CPUs on Odroid-XU3 board.

    Rem
    Rem

    Hello,

    I did experiments with Odroid XU3. I have noticed interesting effect of square root calculation.

    I have received unexpected results, during experiments with execution time of 50 million square root operations.

      double temp = 5.0;
    
      double…
    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 下neon vld指令受memory/cache影响的探讨

    scott meng
    scott meng

    在使用汇编优化neon时,发现一个问题:

    假设函数的输入两个参数x[2048],y[2048],那么x,y的首地址是不连续的

    当在汇编中只读x的数据时所用时间明显比即读取x,也读取y的数据要长很多,我猜想是由于cache没有高效利用的原因,即造成了hit miss的现象,有什么方法可以尽可能的利用cache呢?

    汇编代码如下:

    只读取x

        vld1.32    {d0-d1}, [r0]!

        vld1.32    {d2-d3}, [r0]!

    读取x,y

        vld1.32    {d0-d1}, [r0…

    • over 2 years ago
    • 中文社区
    • 中文社区论区
  • L1 data cache and unified cache disabled in AMP mode for Cortex-a7

    Ashwin
    Ashwin

    Hello Guys,

    in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found though cortex-a7 MPCore TRM is that , those L1 data…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • EGX, eSports and the Mobile Gaming Boom in Asia

    Ben Walshe
    Ben Walshe

    Anyone with an interest in gaming or eSports will know of the UK's biggest games event, EGX, which took place from the 21st to the 24th of September in Birmingham City, UK. Of course there was way too much happening to capture it all, but some of the…

    • over 3 years ago
    • Graphics and Gaming
    • Graphics and Gaming blog
  • Cortex-A7 Generic Timer Clock and Operation

    Sajjad Ahmed
    Sajjad Ahmed

    Hi,

         I'm using NXP imx6ul-evk(single core cortex-a7 processor) and I'm trying to operate CPU at different frequencies(642MHz, 480MHz, 100MHz, 12MHz) and experiencing time drift on certain frequencies (Generic Timer's time lags Real Time), I'm using virtual…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Raspberry Pi 2 JTAG error on memory access

    Alessandro
    Alessandro

    Hi all,

    I am trying to connect to the RPi2 JTAG.

    I have the following setup

    - Raspberry Pi 2 running Raspbian 8.0 (Jessie)

    - OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.

    I setup the GPIO in order to expose the JTAG interface and the…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 Timer寄存器访问

    Senyan
    Senyan

    大家好,我在读取Cortex-A7 Timer的Physical Counter Register(CNTPCT)时遇到一个问题。 根据手册这个寄存器是通过CP15进行访问的,CRm=14,op1=0,长度是64bit。

    我的代码是 mcrr p15, 0, r0, r1, c14。然而在执行时却被当作了Undefined Instruction。 在手册里的确提到了Undefined Instruction是MCRR可能的一种结果,但没有具体解释。

    根据手册,在访问这个寄存器之前,已经在monitor…

    • over 4 years ago
    • 中文社区
    • 中文社区论区
  • Can't find many microprocessor manufacturers with Cortex-A7 architecture?

    Omid
    Omid

    My understanding is that ARM Cortex-A7 architecture was released after Cortex-A9 and improves features of previous versions. However, I have only found one manufacturer, NXP, that uses Cortex-A7 architecture in their processors. I am referring to manufacturers…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure L2 cache in Cortex-A7

    Cherma Rajan
    Cherma Rajan

    Hi all,

    I am working on OrangePi board. The board configuration is,

    • Quad-Core ARM Cortex-A7, 1.6 GHz
    • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
    • 512 KB L2-Cache

    I have few queries related to Cache memory,

    1. How to disable L2 cache of Cortex-A7 in…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Read allocate will impact bzero performance or not

    Ron
    Ron

    I'm trying to understand read allocate mode in cortex A7 core. From description of Read allocate mode in TRM of Cortex A7 core, my understanding is that bzero will downgrade memset performance while memset was done with consecutive memory.  For example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • NE10-Library -> FIR-Filter cycle counts: C-version faster than NEON-version?

    CFriebel
    CFriebel

    Hi,

    i'm currently trying to measure cycle counts for FIR-filtering with the NE10 library. I'm using a Raspberry Pi 2 with ARM Cortex-A7 running on Raspbian as a target.

    I activated the Cortex-A7 performance counter register to read out the cycles…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • what are the main differences between cortex A7, A9, A53

    aaa
    aaa

    What are the main/important features added/updated?

    Thank you.

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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