• Interrupts not received in secure world for Cortex A7 in Trsuty

    Asmaa
    Asmaa

    Hello Everyone,

    I am working on a Microcontroller from NXP - imx7D. We have recently ported Trusty on it. I have written an SPI and a GPIO driver in trusty. When I started testing on it, I realised I am not getting any interrupts in the Secure world i…

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • [Cortex-A7][SMP][Cache]在多核上跑多任务会出现卡死问题

    digtoana
    digtoana

    运行环境:Linux

    现象:

    1. 只跑一个cpu时, 运行多个进程没有问题。

    2.开启SMP后, 四个CPU能正常启动,但是一旦跑多任务(后台多起几个程序),就会百分之百卡死,不进异常。

    3.开启SMP后,关闭L1/L2 Dcache后,按照同样方法跑多任务,就不会卡死。

    看起开好像是cache一致性问题,请教大家有没有什么好的想法和debug手段?

    • 5 months ago
    • 中文社区
    • 中文社区论区
  • -print-libgcc-file-name gives thumb while -marm is used

    Arjan
    Arjan

    Dear Forum,

    Using

    ~$ arm-none-eabi-gcc -v                                                                             
    Using built-in specs.
    COLLECT_GCC=arm-none-eabi-gcc
    COLLECT_LTO_WRAPPER=/opt/gcc-arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/9…

    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to read message from particular number ?

    Pooja Todakar
    Pooja Todakar

    hi i am developing one application.

    in that i want read messages from some perticular number.and i want to read sms using AT commands only,so how can i read sms from particular number?

    now my AT commands are

    AT+CMGF = 1

    AT+CMGL="REC UNREAD"…

    • over 1 year ago
    • Software Tools
    • Keil forum
  • How get ARMv7 cache size

    John
    John

    Hi everybody!!

    I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

    In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to avoid bus error while using neon instruction vld2.32 on cortex a7?

    Katta Phani Kumar
    Katta Phani Kumar

    Hi, I am using imx6ul board which has cortex a7 processor. I am using ffmpeg .s files which has assembly code to integrate into our project to speed up the code.  Here is the ffmpeg code in the file mdct_neon.S.

    #include "asm.S"
    .fpu neo…

    • Answered
    • 9335.zip
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using the whole Cortex-A L2 Cache without external memory

    Laurent
    Laurent

    I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

    The CPU boots from an external 4MBytes SPI NOR FLASH chip.

    It has 512 KBytes of L2 cache and 32 KBytes…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Barriers in in-order cores like cortex-A53, A7

    oootha
    oootha

    Hi experts!

    As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
    However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
    But barriers are even used in in-order cpus.
    What is for?
    Can…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SGIs in AMP Configuration with Non-SMP Linux /RTOS

    Shafique
    Shafique

    I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • voltage levels for dvfs

    Hergys
    Hergys

    Hello,

    i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

    Thank you.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MOESI state encoding of Cortex-A7

    Isa
    Isa

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • in arm7tdmi, when FIQ and RIQ occures at same time so how both are executed sequentially,first FIQ and thenIRQ?

    nirav
    nirav

    in arm7tdmi, suppose instruction is being executed and at same time FIQ and IRQ both occur  at same time.now according to priority FIQ will be handled then IRQ  but my question is that how it will handled IRQ after  return from FIQ

    i means…

    • Answered
    • over 4 years ago
    • Processors
    • Classic processors forum
  • ACTLR[1] question in Cortex-A serias SOC

    chinatiger
    chinatiger

    hi, experts:

    I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

    I have some questions about out cache concept in Cortex-A7.
    1. Some program disable outer cache by setting ACTLR[1] = 0.

       So, is it only available with Cortex-A9…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • system requirements

    SGR
    SGR

    what are the minimum hardware requirements to setup wifi on arm-7 processors.

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MRS/MSR (Banked register)

    Juha Aaltonen
    Juha Aaltonen

    What can be accessed by MRS/MSR in user mode?

    In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

    B9.3.10      MSR (Banked register)
    cond  0 0 0 1 0 R 0 0        M1      …
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Bit 22 in some LD/ST instructions (Cortex-A7)

    Juha Aaltonen
    Juha Aaltonen

    I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?

                               22…
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Still more stupid questions on Cortex-A7 instruction set

    Juha Aaltonen
    Juha Aaltonen

    I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

    an answer to in ARMv7-A/R ARM Issue C.

    How is this special?

    LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case…
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Questions about Generic Timer in ARMv8

    wangchj
    wangchj

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?

    Kun.Niu
    Kun.Niu

    If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?

    In cortex-A7 spec, it says" the core hardware will check all instruction fetches and data reads or writes in the cache, although obviously…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Where can I find the cortex-A7 related 8 stages pipeline docments?

    Kun.Niu
    Kun.Niu

    Where can I find the cortex-A7 related 8 stages pipeline docments?

    I have found some docments about this but all are too brief, so I want ask where can I find the detailed docments?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many?

    Kun.Niu
    Kun.Niu

    In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many bytes?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Where can I find the docments about how the ARM cortex-A series pipeline works?

    Kun.Niu
    Kun.Niu

    Where can I find the docments about how the ARM cortex-A series pipeline works?

    Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

    Kun.Niu
    Kun.Niu

    Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

    In other words, each core have the same 37 registers or the 4 cores share the 37 registers?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A series's pipeline is for only one core or for all cores?

    Kun.Niu
    Kun.Niu

    For example, in ARM's related docments says that cortex-A7 support max to 4 cores and cortex-A8 support only one core, and the same time cortex-A7's pipeline is not the same with cortex-A8's pipeline. I want ask the cortex-A7's pipeline is for all the…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    Kun.Niu
    Kun.Niu

    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:

    I want ask the in-order and out-of-order mean what?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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