• Need help with learning resource for ML on ARM based devices

    rsingh
    rsingh

    Hi all,

    I want to be able to write object detection/Machine vision softwares on raspberry/Jetson like devices. Now these are low powered but decently capable devices.

    Im more inclined towards C++ as language of choice as even a couple more fps really…

    • 21 days ago
    • Open Source Software and Platforms
    • Machine Learning forum
  • trustzone memory configuration for cortex-A57

    raks8877
    raks8877

    Hello,

    I am using jetson tx2 development board which has arm cortex a57 processor which uses arm trusted firmware(atf) to boot. Trusty is the secure world operating system provided by atf.

    Following are my questions:

    1) How to configure how much ram…

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • translation table APTable permission problem

    raks8877
    raks8877

    Hello,

    I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault.

    Current steps which i am doing are:

    1) inside kernel space, allocating 2 pointers (say p, q) and allocating…

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • EDSCR err bit set after a write to EDITR

    kka
    kka

    Hi,

    I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

    So I try to follow that to give the state information.

    Cortex-57

    JTAG TCK = 3,788MHz.

    ARM_STATE_AARCH64 is set

    Before Halt state:

    EDPRSR = 0x1

    EDSCR…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Partial register dependency neon

    doofenstein
    doofenstein

    I'm having trouble finding any informations on partial neon register dependencies.

    Take for example the following code:

    ld2 {v0.16b, v1.16b}[0], [x0]
    ld2 {v0.16b, v1.16b}[1], [x1]
    ld2 {v0.16b, v1.16b}[2], [x2]
    ...

    Does the second load have to wait…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Getting Execution Time of progams on armv8_64-bit processors

    abhi.verma
    abhi.verma

    I have written a library for ARMv8-A 64 bit processors (OS- linaro debian). Now I want to time them. I am utilising gcc compiler and on Intel processors I was timing the execution utilising std::chrono high resolution clock. The issue with arm is, it…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone and Hardware virtualization support

    Justin
    Justin

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TrustZone Controller in FVP Cortex57-A Base platform

    Xinwei
    Xinwei

    Hi,

    I start to learn and program TZC-400  in FVP Cortext57-A Base platform with DS-5, and encounter something that I don't understand.

    I start the FVP as non-secure mode by using the paramter "bp.secure_memory = false".  Then I poll TZC's  gate_keeper…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SIGILL in 32bit chroot on Cortex-A57

    Yichao Yu
    Yichao Yu

    I'm getting a SIGILL when running a ARMv6 program in a chroot environment.

    The instruction that triggers it is

    Program received signal SIGILL, Illegal instruction.
    0x000104f0 in f ()
    (gdb) disassemble $pc
    Dump of assembler code for function f:
    => 0x000104f0…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • where can I find the detailed explanation of ARM PMU events?

    alexamy
    alexamy

    Two questions:

    1. Where can I find the detailed explanation of ARM PMU events?

    2. How to know the stall cycles for e.g. icache miss etc.?

    Thanks.


    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Power Management Options in Cortex A

    techguyz
    techguyz

    Hi Experts,

    Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CPUID information about ARMv8 core

    ocean
    ocean

    Hi experts,

    I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER?

    Thanks.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM_V8 instruction Cycles timings

    ranjithkumar ds
    ranjithkumar ds

    Hi, can anyone suggest me how to know the instructions cycle timing of the arm_v8 instructions.does it take more cycles to transmit from neon to basic arm instructions in arm_v8.

    please suggest me how to calculate instruction cycles in arm_v8

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

    박주병
    박주병

    First sorry my english writing level. :-)

    In non-secure world using android system(linux kernel).

    I use big.little core Cortex-A53, Cortex-A57

    I was tested to 2case.

    previous stage.

         1. Linux allocation memory using(malloc or mmap)

    …
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Kay
    Kay

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareability memory attribute

    hostia
    hostia

    Hi ARM experts,

        For shareability attribute, have some confusions:

        1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability attribute is also set. Otherwise…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What type of ARM is used in 10-Gb Ethernet chip?

    Robert
    Robert

    Hi,

    I heard that some 10-Gb Ethenet chip embedded an ARM core. I am curious about what type of ARM (A, M or R) is embedded in such a high speed Ethernet ASIC. I feel that it may be a R series ARM. Is it right? Due to such a high speed data rate, what chip…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reset Management Register Functioanlity in ARM v8

    techguyz
    techguyz

    Hi Experts,

    Does the Reset Management Register will be implemented mandatory or optional for the SoC based on ARMv8 and how it is practically used ?

    Regards,

    Techguyz

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Integrated Debug Functionality in ARM v8

    techguyz
    techguyz

    Hi Experts,

    What are all the list of integrated debug functionalities in ARM v8 which will be affected by the cold and warm resets.

    Regards,

    Techguyz

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • RTOS for ARM A57(NVIDIA Jetson TX2 / TX2i)

    mea
    mea

    Hi all,

    I would like to use RTOS in my project in NVIDIA Jetson TX2 developer kit. But all of them are expensive. And i tried Real-Time Scheduling with NVIDIA Jetson TX2 by installing preempt RT patch. But the patch is not %100 hard real time. And i do…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Vector Table for ARMv8 (cortex A57)

    Ajeesh
    Ajeesh

    Hi,

     

    How do i configure vector table for cortex A-57?

    From the documents - "The vector table has 16 entries, with each entry being 128 bytes (32 instructions) in size. The table effectively consists of 4 sets of 4 entries"

    Also " Virtual…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • ARMv8 Exception level on Startup

    Ajeesh
    Ajeesh

    Hi,

    When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported?

    How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate each exception levels?

    I have to set it such that normally…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • Embedded ARMv8 dev board

    AnthonyPaulO
    AnthonyPaulO

    I'm an arduino guy looking for more power and I'd like to start using the high performance ARM chips such as the A57 and soon the A75, but I'm having an impossible time finding dev boards for anything other than some older ARM chips (I think the highest…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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