Hi Experts,
I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.
I could…
Hi Experts,
I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.
I could…
Hi,
I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.
I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…
从ARM官方网站下载 fast modles 来仿真 Cortex-a53,发现在选择处理器时,没有Cortex-A53 或者ARMv8 这样的选项,导致无法生成想要的license。
有谁能指点下,是现在版本的fast modles 不支持 Cortex-a53,还是我权限问题。
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…
i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2
我们一般默认L1cache为inner cache,L2cache为outer cache。
没有看到很明确的说明,L1,2cache分别属于inner还是outer?
请专家解释下可以根据什么信息明确这点,谢谢!
Hi Experts,
Is there any sample development boards available on Cortex-A72/5x series ?
Regards,
Techguyz
Hello all,
I have a A53 based platform. There are multiple IRQ sources, some of which fire at the same time. To avoid recursive IRQ handler calls, I have disabled IRQs' on entry in IRQ handler and enabled them befor exit. However, at one point, there is…
hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide…
I'm testing GIC and ARM A53 connectivity. I can see that GIC is forwarding the IRQ request and ARM core has received it(shows in ISR reg). However, my IRQ handler is not getting called. Here is how I'm registering it..
void main () {
...
__enable_irq…
Dear ARM Group,
Can we run the A53 cores at different clock speeds?
if YES, How does it effect the complete A53 (L2 cache etc) and system?
if NO, What are the constraints ?
could you please give a detailed description on this?
Thanks,
Ravinder…
hi,
I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.
Could you give me any suggestion about cache invalid? Thanks!
The program…
I would like to know the price of the license or terms for each core Cortex-A53 and the price of a 4-core processor Cortex-A53 is charged. Sorry if misspelled not know much English and I'm writing with Google Translate.
Greetings ...
You are the best…
Dear ARM Forum,
I am working for a ARM Cortex-A53 + Mali based SOC. I am preparing a demo plan for my platform to show Mali-400 functioning with software stack running on Cortex-A53 AARCH64 Linux OS.
Thanks in advance, I hope your Expertise and Experience…
We are interested in developing Board Support Package and Bootloader code for SOCs based on ARMv8 Architecture (A57/A53). Can someone please suggest is Juno Board a good option for it?
We are interested in writing the BSP code for Memory Controller, UART…
Hi,
I read Juno trm, but I didn't find the frequency of GIC-400 in Juno SoC. Because Cortex-A57 and Cortex-A53 operate at diferent frequency and support DVFS, I think that GIC-400 should operate asynchronously with Cortex-A57 and Cortex-A53. This may…
I find the description below from MMU-500 TRM.
Address width
The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address
bus…
Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!
Can DS-5 Streamline be used with RTSM/Fixed models for cortex-A53 processors? If it is possible, what is the procedure ?
I would like to open a new project under DS-5. I want it to have the following code:
int main() {
int a = 7;
int b = 3;
for (int i=0; i < a*b; i++)
a = b+i;…
Hello,
I want to experiment with a storage solution ARM based. Is there any provider actually selling dev kits or consumer boards based on ARM Cortex-A53 or ARM Cortex-A57?
Obviously the main requirement for purchase is the availability of SATA3 ports for…
I'm using the standard firmware with an OpenEmbedded filesystem on a Juno Development Platform
I'm trying to port code that has been compiled using ADS5.8 to a new beta compiler RVDS6.0 (LLVM based).
I have 2 problems:
1. weak function
I got the following error during linking:
Error: L6654E: Rejected Local symbol [Anonymous Symbol] referred to…
hi, experts:
根据CA57 TRM:
它的地址线数目:
Aarch64 state : 44根
Aarch32 state : 40根
Aarch32 state比Aarch64少用了4根:那么这4根地址线,在Aarch32下,用作什么signal pin?实现相关吗?
best wishes,
As the days get shorter and the cold weather begins to creep in, we know it’s that time of year when we can start to get excited about the brand new devices for the upcoming year. A major announcement for us in the ARM® Mali™ Multimedia team is the brand…