Hi,
Linux Kernel 4.9
Processor a53
SMP 64 Bit linux image
Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts.
moving ethernet interrupts to other core via smp_affinity…
Hi,
Linux Kernel 4.9
Processor a53
SMP 64 Bit linux image
Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts.
moving ethernet interrupts to other core via smp_affinity…
We want to implement 3x3 convolution of image whose size is 4032x3024 on S7/Note7 to have Chipset such as Exynos 8890(S7 S.LSI) or Qualcomm MSM8996 Snapdragon 820.
To implement this, we used the Anroid NDK, Neon SIMD and OpenMP.
For 1 image (4032x3024…
I build a system based on Allwinner H6 SoC which is ARM Cortex A53 core + MALI T720
My project requires GPU: OpenGL ES and OpenCL So I need libMali.so GPU driver for MALI T720
On product page developer.arm.com/.../user-space
I didn't fiund corresponding…
Hi ,
I am looking for someway of using the armNN SDK on a Xilinx Zynq Platform which has Quad-core ARM® CortexTM-A53 MPCoreTM up to 1.5GHz and an ARM MALI 400 MP2 GPU. With ARM Mali GPU noted off in a previous question my next task is to look into if…
I am trying to test my android app which has OpenCL native code. I have Huawei P10 which has Android Nougat. It has Cortex A53 & Cortex A73 CPUs and Mali G71 bifrost GPU. I could not link libOpenCL.so at runtime as its always showing linker failure error…
I'm investigating a input file of linker script for ARM Cortex-A53. It's really difficult for me about syntax and section defined into the scatter script file.
I don't know where to define the input sections, like .fini, .interp, .gnu.linkonce…
I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.
The code has no FPU use so it is supposed to be just a lazy save and restore registers.
The restore section…
I am using arm-none-eabi-* (7 2018-q2-update) to link with newlib-nano to use the NE10 library in a bare metal envirolment.
It looks like i am unable to be successful in compiling the code with newlib nano as i get many undefined references. I have messed…
Do Arm offer A53 with only MPU? Because right now we have only one to one mapping. we just need to use MPU only. Yes I understand MMU is superset of MPU but can be expensive (performance wise). Or there other way to use MMU?
Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.
so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…
Hello!
I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the Cortex A53s and the FPGA utilizing the built in ARM…
Home many performance monitoring units (PMU) are in ARM Cortex A-53 and A-9? Is there a single PMU for each core or single PMU for the whole processor?
Hi,
Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when…
Hi experts,
Recently, I'm trying to evaluate the code execution time when using the A53 core and the A57 core.
However, my result shows A53 core is much faster than the A57 core, which does not make sense to me so I want to share my case here to see…
I am working with an S32V234 (NXP) branded ARMv8 Cortex-A53. I am trying to bring the board up in a secure way.I'm using DS-5 Development Studio Ultimate edition.I created a sample C Project. For flashing my code on that ARM Core.Firstly I Configured…
Hello,
I want to write a bit-banging driver for a Raspberry Pi 3 (Cortex A53 with 4 cores).
For testing I developed a simple Linux kernel mode driver which toggles a GPIO pin with approx. 1Mhz.
In order to get no interference by the Linux kernel I disabled…
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All consumers have premium tastes. These days, we demand more of our phones than ever. Where once they were just for calling and texting, now we expect to be able to surf social…
Hi all,
I noticed there are multiple system control registers in ARM.
The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.
I want to know, what do multiple such system controls registers represent??
I am particularly interested in the A bit of the system control register…
Hi all,
I am working with a simple sqrt kernel. Code given below at end of post. It calculates the sqrt on a given array and stores it into a new array.
However, when compiling with a gcc compiler as - gcc -mcpu=cortex-a53 -mfpu=neon neon_sqrt_kernel.…
Bare metal software is used for benchmarking, developing software algorithms, comparing different compilers, and developing startup code. Arm DS-5 comes with many examples of bare metal software, especially for CPU initialization. Arm Cycle Models also…
Hi All,
I am using Arm Cortex-A53 based board.I modified a driver module and the interrupt processing.
I have a fundamental question:
Since Arm Cortex-A53 can handle 16 primary interrupts, what happens if all the interrupts arrive at same time. Though…
Authors: Jim Wallace, Arm; Joseph Byrne, NXP
Service providers or anyone involved in building out next-generation networks are faced with complex challenges today as they seek to evolve, future-proof, and secure their networks to meet the ever-increasing…
Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…
CA53 run 32bit linux kernel, 发现arch/arm/kernel/perf_event_v7.c 只支持ARMv7 的 ca17, ca15, ca12, ca9, ca8, ca7, ca5 的PMU. 没有ca53.
不知道是否可以直接使用 ARMv7的所支持的CPU呢?
Hi Experts,
I have a question about "STP" instruction in Cortex-A53.
STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.
I don't know why cause it.
Can you help to explain the reason…