• interrupt distribution on A53 processor

    RCReddy
    RCReddy

    Hi,

         Linux Kernel 4.9

         Processor a53

          SMP 64 Bit linux image

    Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts.

    moving ethernet interrupts to other core via smp_affinity…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • 3x3 convolution optimized speed using (NEON SIMD) or (NEON SIMD and OpenMP) on S7/Note7

    jaeho
    jaeho

    We want to implement 3x3 convolution of image whose size is 4032x3024 on S7/Note7 to have Chipset such as Exynos 8890(S7 S.LSI) or Qualcomm MSM8996 Snapdragon 820.
    To implement this, we used the Anroid NDK, Neon SIMD and OpenMP.
    For 1 image (4032x3024…

    • over 4 years ago
    • Open Source Software and Platforms
    • Android forum
  • Wher ts the Midgard T720 MALI userspace driver for linux available?

    Yaroslav-Korchevsky
    Yaroslav-Korchevsky

    I build a system based on Allwinner H6 SoC which is ARM Cortex A53 core + MALI T720

    My project requires GPU: OpenGL ES and OpenCL So I need libMali.so GPU driver for MALI T720
    On product page developer.arm.com/.../user-space
    I didn't fiund corresponding…

    • Answered
    • over 2 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Cross-Compile ArmNN on x86_64 for arm64

    fatimak
    fatimak

    Hi ,

    I am looking for someway of using the armNN SDK on a Xilinx Zynq Platform which has Quad-core ARM® CortexTM-A53 MPCoreTM up to 1.5GHz and an ARM MALI 400 MP2 GPU. With ARM Mali GPU noted off in a previous question my next task is to look into if…

    • Answered
    • over 2 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Can Mali G71 GPU be tested on Huawei P10 android mobile?

    jothi-92
    jothi-92

    I am trying to test my android app which has OpenCL native code. I have Huawei P10 which has Android Nougat. It has Cortex A53 & Cortex A73 CPUs and Mali G71 bifrost GPU. I could not link libOpenCL.so at runtime as its always showing linker failure error…

    • Answered
    • over 3 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Scatter file format for Linker Script

    nhivp
    nhivp

    I'm investigating a input file of linker script for ARM Cortex-A53. It's really difficult for me about syntax and section defined into the scatter script file.

    I don't know where to define the input sections, like .fini, .interp, .gnu.linkonce…

    • Answered
    • over 3 years ago
    • Software Tools
    • Arm Development Studio forum
  • Cortexa53 AARCH64 context switch

    LdB
    LdB

    I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.

    The code has no FPU use so it is supposed to be just a lazy save and restore registers.

    The restore section…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Linking with newlib for NE10 library

    Sheroy
    Sheroy

    I am using arm-none-eabi-* (7 2018-q2-update) to link with newlib-nano to use the NE10 library in a bare metal envirolment.

    It looks like i am unable to be successful in compiling the code with newlib nano as i get many undefined references. I have messed…

    • over 2 years ago
    • Open Source Software and Platforms
    • Android forum
  • A53 - MMU vs MPU

    Umang Mehta
    Umang Mehta

    Do Arm offer A53 with only MPU? Because right now we have only one to one mapping.  we just need to use MPU only.  Yes I understand MMU is superset of MPU but can be expensive (performance wise).  Or there other way to use MMU? 

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence

    Sandeep Bobba
    Sandeep Bobba

    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

    so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Share aarch64 page tables created by Linux with SMMU

    luk
    luk

    Hello!

    I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the Cortex A53s and the FPGA utilizing the built in ARM…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Number of performance monitoring units in ARM Cortex A-53 and A-9

    user
    user

    Home many performance monitoring units (PMU) are in ARM Cortex A-53 and A-9? Is there a single PMU for each core or single PMU for the whole processor?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Barrier after access to memory mapped register?

    dedoz
    dedoz

    Hi,

    Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Juno A57 Core Runs Slower Than A53 Core

    Shengye Wan
    Shengye Wan

    Hi experts,

    Recently, I'm trying to evaluate the code execution time when using the A53 core and the A57 core.

    However, my result shows A53 core is much faster than the A57 core, which does not make sense to me so I want to share my case here to see…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Cortex A53 Debug using DSTREAM

    premchandh
    premchandh

    I am working with an S32V234 (NXP) branded ARMv8 Cortex-A53. I am trying to bring the board up in a secure way.I'm using DS-5 Development Studio Ultimate edition.I created a sample C Project. For flashing my code on that ARM Core.Firstly I Configured…

    • over 2 years ago
    • Software Tools
    • Arm Development Studio forum
  • Reason for Cortex A53 delays

    urian
    urian

    Hello,

    I want to write a bit-banging driver for a Raspberry Pi 3 (Cortex A53 with 4 cores).
    For testing I developed a simple Linux kernel mode driver which toggles a GPIO pin with approx. 1Mhz.
    In order to get no interference by the Linux kernel I disabled…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • New Samsung Exynos 7 Octa 7870 brings premium performance to mass market mobile

    Eoin McCann
    Eoin McCann

    Chinese Version 中文版:三星全新Exynos 7 Octa 7870 为大众手机提升品质

    Addressing premium tastes

    All consumers have premium tastes. These days, we demand more of our phones than ever. Where once they were just for calling and texting, now we expect to be able to surf social…

    • over 4 years ago
    • Processors
    • Processors blog
  • Information about ARM System control registers.

    aketh
    aketh

    Hi all,

    I noticed there are multiple system control registers in ARM.

    The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

    I want to know, what do multiple such system controls registers represent??

    I am particularly interested in the A bit of the system control register…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • NEON intrinsics vector division and reciprocal functions not found

    aketh
    aketh

    Hi all,

    I am working with a simple sqrt kernel. Code given below at end of post. It calculates the sqrt on a given array and stores it into a new array.

    However, when compiling with a  gcc compiler as  - gcc -mcpu=cortex-a53 -mfpu=neon neon_sqrt_kernel.…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Running bare metal software on the Raspberry Pi 3 using Arm DS-5

    Jason Andrews
    Jason Andrews

    Bare metal software is used for benchmarking, developing software algorithms, comparing different compilers, and developing startup code. Arm DS-5 comes with many examples of bare metal software, especially for CPU initialization. Arm Cycle Models also…

    • pi3-bm-sort.zip
    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Interrupt collector

    RCReddy
    RCReddy

    Hi All,

    I am using Arm Cortex-A53 based board.I modified a driver module and the interrupt processing.

    I have a fundamental question:

    Since Arm Cortex-A53 can handle 16 primary interrupts, what happens if all the interrupts arrive at same time. Though…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm partnership providing the foundation for next generation networks

    Jim Wallace
    Jim Wallace

    Authors: Jim Wallace, Arm; Joseph Byrne, NXP

    Service providers or anyone involved in building out next-generation networks are faced with complex challenges today as they seek to evolve, future-proof, and secure their networks to meet the ever-increasing…

    • over 2 years ago
    • Processors
    • Processors blog
  • ARM cortext A53 Physical Address Flush

    m0sf3tz
    m0sf3tz

    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [PMU]Cortex-A53 使用AArch32 Kernel, 可以直接使用Linux Kernel自带的arm,cortex-a7-pmu吗?

    magicse7en
    magicse7en

    CA53 run 32bit linux kernel, 发现arch/arm/kernel/perf_event_v7.c 只支持ARMv7 的 ca17, ca15, ca12, ca9, ca8, ca7, ca5 的PMU.  没有ca53. 

    不知道是否可以直接使用 ARMv7的所支持的CPU呢?

    • over 2 years ago
    • 中文社区
    • 中文社区论区
  • [Cortex-A53] STP instruction stores out of the specified memory

    Emmy0
    Emmy0

    Hi Experts,

         I have a question about "STP" instruction in Cortex-A53.

         STP W6, W6, [SP, #20]  --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.

         I don't know why cause it. 

        Can you help to explain the reason…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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