I am testing armnn+compute library on my RK3399. I want to measure the inference time using only the A53 cores. How can I exploit Compute Library functionalities to do so?
I am testing armnn+compute library on my RK3399. I want to measure the inference time using only the A53 cores. How can I exploit Compute Library functionalities to do so?
Dear Experts,
I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.
I have tried to include in the Linux kernel code (at kernel/init/main.c) a call…
I am failing at searches can someone point me to a reference for the banked registers for an FIQ in AARCH64 on a cortexA53
I can find hundreds of references for AARCH32 banked registers but none for AARCH64
I have largely ignored the FIQ to date just…
Hi All,
i went through this link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
and related a53 vector table implementation.
in this regard, i have a question
1. Say a processor gets stuck in exception handler due…
Hi,
I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.
I'm writing bare-metal code, without…
Hi,
I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…
For one of our devices (which uses ARM A53 Core with GICv2) we need to configure one of the interrupt sources as FIQ at EL1.
So is there any support for doing such a thing preferably in any of the branches of linux kernel.
when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!
Dear all,
I want to debug our Soc chip with DS-5 tool, the SoC has two Cortex-A53 cores.
When I debug Bare-metal code in DS-5, I only can debug one of two A53 with Bare-metal code ,
Any one of two A53 can run exactly. When I debug two A53 at the same time…
Hi,
How do i configure vector table for cortex A-57?
From the documents - "The vector table has 16 entries, with each entry being 128 bytes (32 instructions) in size. The table effectively consists of 4 sets of 4 entries"
Also " Virtual…
Hello,
I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.
The algorithm involves many calculations of FFT and matrix using. As highest priority, we…
We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not getting any interrupts. How to make interrupts work…
Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.
In our watch point handler, we first disabled watch point control, then handle debug…
Hi All,
a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.
how to implement a suspend/resume flow on a individual core?
TRM only mentions about how to clean cache and off-line from smp
But how to do a cache flush through…
Which is better of thees CPUs:
Cortex A53 octa core 1.5 ghz,
Cortex A7 Allwinner T8 Eight core 2.0 ghz,
Cortex A9 Quad-Core 1.8 ghz ?
Hi,
I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.
My question is how should I interpret the shareability domain: inner, outer…
Hi,
I am reading the A53 MP Core doc.
My question is related to instruction preloading in aarch64.
In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.
Question 1: Will the PLI instruction first…
We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here?
regards,
Ravi
Hi,
I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.
The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.
There is no L3 cache. So the memory…
Hi ,
If I generate the elf file from the Default bootcode and pagetables , I get a very small size but
after mapping the Stack pointer to SRAM , I am getting a huge HEX file.
Here is the loader file code
============================================…
Hello experts,
In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations…
Hi,
The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…
Hi,
Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How is it different from Generic timer…
We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.
While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…