• Cortex-A53 : complex array problem

    BatuhanBulut
    BatuhanBulut

    Hello ;

    I am working on Arm Cortex-A53 and here is the problem;

    when ı am trying to allocate

      A= new comp[N]; >>

    typedef std::complex< double > comp;>>

    #include <complex>

    struct complex<double>
    {
    typedef double value_typ…

    • 8 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

    krjdev
    krjdev

    Hello,

    I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :(

    I created following tables:

    Level 1

    0   0000000010006003                             
    1   0000000010007003 
    2   0000000010008003                    …

    • Answered
    • 1 month ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 switching from EL2 to EL1

    krjdev
    krjdev

    Hi,

    I trying to switch from EL2 to EL1 on Cortex-A53. But it doesn't work.

    Here is my current startup code:

    #include <asm.h>
    
    IMPORT_ASM(_cpu_el3_vec_tbl_set)
    IMPORT_ASM(_cpu_el2_vec_tbl_set)
    IMPORT_ASM(_cpu_el1_vec_tbl_set)
    
    IMPORT_C(init…

    • 1 month ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to enable VFP feature in cortex a53 64bit kernel for armv7 architecture

    William Jacob
    William Jacob

    Hi,

    I got the below"cpuinfo" information in my cortex a53 machine. Can you tell if VFP feature is enabled in my machine ? If it is not enabled, how to enable VFP for 64bit kernel.

    $cat /proc/cpuinfo
    processor : 0
    BogoMIPS : 50.00
    Features : fp…

    • 2 months ago
    • System
    • Embedded forum
  • Using a 32bit libray in ArmV8 applicatio

    Santhosh-K-M
    Santhosh-K-M

    Hello Sir,
    We are using the liaro's aarch64-linux-gnu-gcc compiler, (version = gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu) for cross compiling for armv8, Cortex A53. We use many libraries, one of them is openssl-1.0.1p which supports max till armv7…

    • Answered
    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Debug using gdb debugger, how to get the exception level?

    Boon Khai
    Boon Khai

    I'm debugging the ARM Cortex A53 on the QEMU emulator using gdb debugger, any idea on how to get what exception level I'm running on (EL3/2/1/0) ?

    • Answered
    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Correct Cross Toolchain

    QAZ
    QAZ

    Hi.

    Could you please identify the correct GNU toolchain at the below link which will compile my Linux application to be built using Arm DS running on Windows targeting a Cortex A53 running embedded Linux. The link is developer.arm.com/.../downloads. Thanks…

    • 5 months ago
    • Open Source Software and Platforms
    • GNU Toolchain forum
  • How to know why system hangs in EL2

    irakatz
    irakatz

    Hello,

    I am trying to enable stage 2 translation on Raspberry Pi 3B+. I create a translation table, store its base address in VTTBR, configure VTCR and HCR to enable stage 2 translation.

    These steps should be finished in EL2, but it hangs, without any…

    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • imx-atf boot flow

    segfault
    segfault

    Hi,

    imx-atf allows alternative boot flow by preloading a BL33 (custom) image into memory.

    Are there any instructions on how to use BL2 to boot an EL3 payload for pre-production test work ?  How to use EL3_PAYLOAD_BASE common build parameter ?

    Also, there…

    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Booting of cortex M7 core, independently of cortex A53 core

    AnuragDoshi
    AnuragDoshi

    I have a development board of NXP that has 4 x A53 cores and 1 x M7 core. I want to run 2 different OSes on the boards that are independent of each other. And my goal is to boot the processors separately without having dependence of the other core for…

    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Arm Trusted firmware as bootloader for A53

    segfault
    segfault

    Hi,

    I can build bl31.bin for my i.MX8QM EVK (Arm Trusted Firmware open source reference) which can act as an Armv8-A bootloader.

    I am NOT intending to include any u-boot binary in my test image.  Is this possible ?

    Can anyone suggest how to build a Cortex…

    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Inconsistent shareability domain on tlbi instructions

    josecm
    josecm

    I'm using a IMX8QM system which features a dual-core A72 cluster plus a quad-core A53 cluster. Running on EL2 from one of the A53 cores I want to unmap a single page for all cores, so after I remove the entry for the page table I use the tlb invalidation…

    • Answered
    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Development board with Cortex-A53?

    DanijelDomazet
    DanijelDomazet

    Hi Arm community. 

    I'd like to get a development board with Cortex-A53 processor to develop, test and verify some audio algorithms. I'm working on Windows+Cygwin+Eclipse, so the board should be easily used with these tools. It should also be well documented…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Invalid Exception Class

    Killbox
    Killbox

    When debugging my bare metal app I'm getting an exception I don't understand.

    The processor is the Cortex-A53

    The Exception occurs on "str q0, [sp, #96]"

    When reading ESR_EL1 i get 0x1FE00000

    so, the exception class is 0b111111

    which…

    • Answered
    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARMv8-A has VC_CORERESET or something similar?

    Ranjith TC
    Ranjith TC

    Hi All.

    Does ARMv8-A has something similar to VC_CORERESET bit in Debug Exception and Monitor Control Register of ARMv8-M ; which enables halt on reset vector on warm reset?
    Or is there any other method to halt the ARMv8-A core in reset vector?

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • performance of floating point

    jinhong
    jinhong

    hi.

    I have a question about floating point performance relative with fpsr register.

    When i initialize hardware, there is floating point exception(inexactly floating-point exception).

    I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.

    …
    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • GNU Toolchain - Unknown or missing system register (GIC register - Cortex-A53)

    krjdev
    krjdev

    I have started a simple bare-metal project for the Cortex-A53. Now I want to implement interrupt handling, but run into an issue with the toolchain.

    Want to read out and write into the ICC_x registers, but get the following error message from GAS:

    $…

    • Answered
    • 8 months ago
    • Open Source Software and Platforms
    • GNU Toolchain forum
  • [Cortex-A53] Exception Syndrome Register - Exception Class

    krjdev
    krjdev

    Hi,

    I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information.

    Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64 (quad core Cortex-A53) board, which I want

    …
    • Answered
    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 Bare metal booting have FIQ exception. How to debug?

    Ben Chen
    Ben Chen

    Hi

    I study coresight test with cortex A53 CPU.

    I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

    I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

    Set CPU config pin aa64naa32 to 1…

    • Answered
    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache clean of translation tables stops execution?

    Richard Kraus
    Richard Kraus

    Hi,

    I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

    Now I am trying to hook the pagefault…

    • 9 months ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • A53 Erratum 820719 missing from official ARM errata document list

    ekta
    ekta

    There is a reference to erratum 820719 in the NXP S32V Errata list but I can't seem to find any reference to this erratum anywhere in ARM documentation. Is this erratum still valid?

    Excerpt from S32V Errata document (refer: https://www.nxp.com/docs…

    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53

    khan777
    khan777

    Hi,

    I am using IDE Xilinx SDK 2019.1 for my application and running it on ARM cortex a53  processor with Neon and floating point engine support available. I am working on a bare metal application.

    The problem I am facing is that, I am unable to understand…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)

    khan777
    khan777

    I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

    I tried -mfpu…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Optimization of Neon Intrinsics on ARM cortexa53

    khan777
    khan777

    I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?

    Here is the code:

    static inline…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Resetting GIC by SW?

    kabel
    kabel

    Hello,

    we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500.

    The M3 has access to all registers that A53 can see. The first A53 has RVBAR at 0xffff0000 where…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
>