• A9 Code after vector table

    josecm
    josecm

    I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Yeli
    Yeli

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to know if a RAM is compatible with an architecture or a processor?

    wchgoldbach
    wchgoldbach

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use neon libraries ?

    TheLazy
    TheLazy

    Hi,

    I am working on an optimization project on Udoo board. I have to optimize a video shot detection code to work in real time. My Udoo board has i.Mx6 Cortex-A9 processor. I started working on optimization and have optimized the code upto 135ms per frame…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Load / Store timings with different cache settings

    superdesk
    superdesk

    Hello,

    I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program on a single core of a Cortex-A9 on a Xilinix Zynq-7000…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using PMU on cortex-a9 CPU

    wagner
    wagner

    Folks,

    I am trying to run linux 'perf' on a new board with 2 ARM cortex-a9 CPUs. After compiling the kernel to include perf tool, i run 'perf stat true' and it returns valid stats. But when I run 'perf record' to profile my program, it doesn't record…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can't find many microprocessor manufacturers with Cortex-A7 architecture?

    Omid
    Omid

    My understanding is that ARM Cortex-A7 architecture was released after Cortex-A9 and improves features of previous versions. However, I have only found one manufacturer, NXP, that uses Cortex-A7 architecture in their processors. I am referring to manufacturers…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 SCU Control Register Enable bit 0 or 1 for enable changed in Manual from g to h?

    NOTAN
    NOTAN

    The Cortex-A9 MPCore Technical Reference Manual Revision: r4p1

    describes the Bit 0 of scu-control-register  as   0 SCU enable 1 SCU disable. (this is Version i of the manual)

    In Version g of the manual ist the other way round (1 SCU enable 0 SCU disable)…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Pipeline and Reorder Buffer on Cortex A9

    andTo
    andTo

    Hi everyone,


    For research reasons, I'm looking for information about the Cortex A9 out-of-order pipeline and the renaming of registries and any other data structures, if any, such as the reorder buffer (ROB).

    The Technical Reference Manual only names…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Number of performance monitoring units in ARM Cortex A-53 and A-9

    user
    user

    Home many performance monitoring units (PMU) are in ARM Cortex A-53 and A-9? Is there a single PMU for each core or single PMU for the whole processor?

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

    teamrtos
    teamrtos

    Hi

    I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core.  Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • DS-5 Bare-metal code - Accessing my host NIC card drivers

    Ab
    Ab

    Hi there, 

    Is there any way from DS-5 development studio to access my host NIC ethernet card? 

    I want to write a bare metal code (Cortext A9),  creating an ARP packet on DS-5 and I would like to test it if its working with my host NIC Card drivers. 

    Is it…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Download Eclipse in Embedded Boards (Arm Processeur)

    kanzali
    kanzali

    Hi ,

    Please I need help, I need to download Eclipse in My board DE1-Soc FPGA Which has the latest dual-core Cortex-A9 embedded cores with architecture armv7l and the other board Rasberry ARM Cortex-A53.

    do you have any idea which packages can I install…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • The process of initializing ddr and other things on Cortex-A9

    Dean_Runov
    Dean_Runov

    Good afternoon!

    I work with Cortex-A9 and try to load the primary bootloader through the JTAG ARM-USB-TINY-H. For download, I need to know the sequence of entries in the registers to initialize the ddr, pll,uart. Where can I find the source to see all this…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMP system on Cortex-A9. How to do it?

    pinchazer
    pinchazer

    Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…

    • over 3 years ago
    • System
    • SoC Design forum
  • Is it possible at all to inspect DCACHE line bytes (and flags) on the Cortex-A9 core by reading/writing CP14 or (less likely CP15)?

    Lukasz
    Lukasz

    I'm trying to fix problems related to Dcache enabling on Cortex-A9 based board.

    Is it possible to inspect cache line data? How I should do it? Shall I use CP14?

    I do know that with Lauterbach's TRACE32 it was possible to modify and inspect cache content…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Mali 400 driver integration guide

    TJeruzalski
    TJeruzalski

    Hi to all!

    I've been working on getting mali 400 to work on my rk3066 device, but no luck. I'm trying to understand how to implement complete kernel-side drivers (ump secure id, modifications to rk framebuffer driver). That would be great if anyone can…

    • over 3 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
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