• Ways to Tx data from Cortex R5 to A53?

    Zombie_Ashish
    Zombie_Ashish

    Hello,

    I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • GIC500 + CPU Interface - CA53

    Ryan100
    Ryan100

    Hi,

    I am triggering PPI or SGI interrupt on gic500 which will then communicate with CA53 over cpu interface and interrupt routine will be executed. 

    After interrupt routine is executed, we can write to cpu interface End Of Interrupt Register to "clear" interrupt…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reason for Cortex A53 delays

    urian
    urian

    Hello,

    I want to write a bit-banging driver for a Raspberry Pi 3 (Cortex A53 with 4 cores).
    For testing I developed a simple Linux kernel mode driver which toggles a GPIO pin with approx. 1Mhz.
    In order to get no interference by the Linux kernel I disabled…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Barrier after access to memory mapped register?

    dedoz
    dedoz

    Hi,

    Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Number of performance monitoring units in ARM Cortex A-53 and A-9

    user
    user

    Home many performance monitoring units (PMU) are in ARM Cortex A-53 and A-9? Is there a single PMU for each core or single PMU for the whole processor?

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does the ARM CA53 4 core join NEON on only 2 cores?

    win847
    win847

    Our project only wants 2 cores to support NEON for cost reasons. How can I do this?

    1. Can a single cluster be done?


    2. Cut into 2 clusters, each with 2 cores. What is the difference between the performance of ARM HMP scheduling 4 cores and the performance…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • WT it non cache able memory when it broadcast at transaction

    Reco
    Reco

    when we says "Cortex-A53 processor simplifies the coherency logic by downgrading memory to non Cache able if it is marked as Inner Write-Through or outer Write though" what is excatly this means ..Is CA53 treats WT memory as non cache able ?…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence

    Sandeep Bobba
    Sandeep Bobba

    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

    so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-R / R-Profile forum
  • How to enable L2 cache view for A53 on Juno ADP r0?

    Marc
    Marc

    Hello,

    I have used DS-5+DSTREAM to connect to the A57/A53 big.LITTLE clusters on my Juno dev board. I use the startup_ARMv8_GICv2 example project included with DS-5 as the bare-metal image to run.

    When I navigate to the cache view window in DS-5, I can…

    • Answered
    • 10999.zip
    • over 4 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Juno r2 L2 and TLB cache

    xpo
    xpo

    Hey guys,

    I need your help because I have to count the number of L2 instruction access, miss and hits. But in the data-sheet I did not find the events that I have to count.

    I found it in the ARM V8 data-sheet. Therefore, is it usable on A72 & A53 even…

    • Answered
    • over 3 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • How to use the external debugging interface in Juno board?

    Zhenyu Ning
    Zhenyu Ning

    Hi all,

    I am trying to use one Cortex-A57 (debugger) core to debug a Cortex-A53 core (target) on Juno board. According to the armv8 architecture manual, i may halt the the target and use EDITR instruction to force the target execute instructions. So,…

    • Answered
    • over 3 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • NEON intrinsics vector division and reciprocal functions not found

    aketh
    aketh

    Hi all,

    I am working with a simple sqrt kernel. Code given below at end of post. It calculates the sqrt on a given array and stores it into a new array.

    However, when compiling with a  gcc compiler as  - gcc -mcpu=cortex-a53 -mfpu=neon neon_sqrt_kernel.…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Download Eclipse in Embedded Boards (Arm Processeur)

    kanzali
    kanzali

    Hi ,

    Please I need help, I need to download Eclipse in My board DE1-Soc FPGA Which has the latest dual-core Cortex-A9 embedded cores with architecture armv7l and the other board Rasberry ARM Cortex-A53.

    do you have any idea which packages can I install…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Juno A57 Core Runs Slower Than A53 Core

    Shengye Wan
    Shengye Wan

    Hi experts,

    Recently, I'm trying to evaluate the code execution time when using the A53 core and the A57 core.

    However, my result shows A53 core is much faster than the A57 core, which does not make sense to me so I want to share my case here to see…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Can Cortex-A53 be used in lock-step mode?

    MONIKA
    MONIKA

    Can Cortex-A53 be used in lock-step mode? There are many references for Cortex-R5 being used in lock step mode , could not find any information about Cortex-A53 , Can you please help

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 Out of Order?

    Hisenberg
    Hisenberg

    Hi all,

    Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first do PLL init. Strange point is that the PLL init…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • interrupt distribution on A53 processor

    RCReddy
    RCReddy

    Hi,

         Linux Kernel 4.9

         Processor a53

          SMP 64 Bit linux image

    Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts.

    moving ethernet interrupts to other core via smp_affinity…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • 3x3 convolution optimized speed using (NEON SIMD) or (NEON SIMD and OpenMP) on S7/Note7

    jaeho
    jaeho

    We want to implement 3x3 convolution of image whose size is 4032x3024 on S7/Note7 to have Chipset such as Exynos 8890(S7 S.LSI) or Qualcomm MSM8996 Snapdragon 820.
    To implement this, we used the Anroid NDK, Neon SIMD and OpenMP.
    For 1 image (4032x3024…

    • over 4 years ago
    • Open Source Software and Platforms
    • Android forum
  • Mali-400 functioning with software stack running on Cortex-A53 AARCH64 Linux OS.

    Ravinder
    Ravinder

    Dear ARM Forum,


    I am working for a ARM Cortex-A53 + Mali based SOC. I am preparing a demo plan for my platform to show Mali-400 functioning with  software stack running on Cortex-A53 AARCH64 Linux OS.

    Thanks in advance, I hope your Expertise and Experience…

    • Answered
    • over 5 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Wher ts the Midgard T720 MALI userspace driver for linux available?

    Yaroslav-Korchevsky
    Yaroslav-Korchevsky

    I build a system based on Allwinner H6 SoC which is ARM Cortex A53 core + MALI T720

    My project requires GPU: OpenGL ES and OpenCL So I need libMali.so GPU driver for MALI T720
    On product page developer.arm.com/.../user-space
    I didn't fiund corresponding…

    • Answered
    • over 2 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Cross-Compile ArmNN on x86_64 for arm64

    fatimak
    fatimak

    Hi ,

    I am looking for someway of using the armNN SDK on a Xilinx Zynq Platform which has Quad-core ARM® CortexTM-A53 MPCoreTM up to 1.5GHz and an ARM MALI 400 MP2 GPU. With ARM Mali GPU noted off in a previous question my next task is to look into if…

    • Answered
    • over 1 year ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Can Mali G71 GPU be tested on Huawei P10 android mobile?

    jothi-92
    jothi-92

    I am trying to test my android app which has OpenCL native code. I have Huawei P10 which has Android Nougat. It has Cortex A53 & Cortex A73 CPUs and Mali G71 bifrost GPU. I could not link libOpenCL.so at runtime as its always showing linker failure error…

    • Answered
    • over 3 years ago
    • Graphics and Gaming
    • Graphics and Gaming forum
  • Scatter file format for Linker Script

    nhivp
    nhivp

    I'm investigating a input file of linker script for ARM Cortex-A53. It's really difficult for me about syntax and section defined into the scatter script file.

    I don't know where to define the input sections, like .fini, .interp, .gnu.linkonce…

    • Answered
    • over 2 years ago
    • Software Tools
    • Arm Development Studio forum
  • Cortex A53 Debug using DSTREAM

    premchandh
    premchandh

    I am working with an S32V234 (NXP) branded ARMv8 Cortex-A53. I am trying to bring the board up in a secure way.I'm using DS-5 Development Studio Ultimate edition.I created a sample C Project. For flashing my code on that ARM Core.Firstly I Configured…

    • over 2 years ago
    • Software Tools
    • Arm Development Studio forum
  • Cortexa53 AARCH64 context switch

    LdB
    LdB

    I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.

    The code has no FPU use so it is supposed to be just a lazy save and restore registers.

    The restore section…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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