• Cortex-A53 - GICv4 Documentation

    anoop
    anoop

    i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    Kun.Niu
    Kun.Niu

    Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

    ca7pipeline.PNGca15pipeline.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to measure program execution time in ARM Cortex-A53 processor?

    Rajeev Verma
    Rajeev Verma

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

    박주병
    박주병

    First sorry my english writing level. :-)

    In non-secure world using android system(linux kernel).

    I use big.little core Cortex-A53, Cortex-A57

    I was tested to 2case.

    previous stage.

         1. Linux allocation memory using(malloc or mmap)

    …
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Kay
    Kay

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 EL1 MMU

    Harish G
    Harish G

    Hi,

        I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

    I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • brk instrustion

    hostia
    hostia

    Hi arm experts,

        I wrote some simple C functions to check if the result of memcpy is expected after enable MMU and data cache on Cortex-A53. The assembly (got by disassembling with aarch64-none-elf-objdump) of the one of these functions…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable attribute in armv8

    Harish G
    Harish G

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CA72 transactions IDs

    Jay Zhao
    Jay Zhao

    In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.

    But in CA72, I can't find such descriptions.

    In my simulation, tt seems that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Exception handlers and interrupt

    RCReddy
    RCReddy

    Hi All,

            i went through this link

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html

    and related a53 vector table implementation.

    in this regard, i have a question

    1. Say a processor gets stuck in exception handler due…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • VMSAv8-64 and spinlock

    Ciro Donnarumma
    Ciro Donnarumma

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable domain and cache policy problem

    zhi
    zhi

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot!

    sam0220
    sam0220

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Vector Table for ARMv8 (cortex A57)

    Ajeesh
    Ajeesh

    Hi,

     

    How do i configure vector table for cortex A-57?

    From the documents - "The vector table has 16 entries, with each entry being 128 bytes (32 instructions) in size. The table effectively consists of 4 sets of 4 entries"

    Also " Virtual…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • ARM Zynq Cortex-A53: implementing complex matrix inversion

    Laurent38
    Laurent38

    Hello,

    I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.

    The algorithm involves many calculations of FFT and matrix using. As highest priority, we…

    • over 2 years ago
    • System
    • Embedded forum
  • Armv8 Memory Mapping

    AnthonyPaulO
    AnthonyPaulO

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the relationship between exclusive access and memory cacheable in Cortex A53?

    Emmy0
    Emmy0

    Hello community and experts,

             I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

             When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can Cortex-A53 l2 cache be controlled seperatly?

    Emmy0
    Emmy0

    Hi Experts,

        I'm researching Cortex-A53 cache.

       Can Cortex-a53 l2cache be enable/disable independently? 

       Is it possible to only enable l1 cache and disable l2cache?

       Does cortex-a53 support l2cache lock function?

       Thanks for your attention!

    Best…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using an external clock - experts only

    AnthonyPaulO
    AnthonyPaulO

    I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Intercore interrupts on a53 between EL1 and EL3

    atr
    atr

    We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not getting any interrupts. How to make interrupts work…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • About watch point debug excption on Cortex-A53

    tao.zeng
    tao.zeng

    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

    In our watch point handler, we first disabled watch point control, then handle debug…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMP to suspend an individual core with security OS

    astonelin@gmail.com
    astonelin@gmail.com

    Hi All,

    a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

    how to implement a suspend/resume flow on a individual core?

    TRM only mentions about how to clean cache and off-line from smp

    But how to do a cache flush through…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareability attribute for armv8 cortex a-53

    MarekBykowski
    MarekBykowski

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A53 preload mechanism

    MarkL
    MarkL

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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