I am looking for a appropriate CortexA15 development board. If the price is less than $1000, or even $500, so much the better
Does anyone have the suggestion with such board?
Thank you!
I am looking for a appropriate CortexA15 development board. If the price is less than $1000, or even $500, so much the better
Does anyone have the suggestion with such board?
Thank you!
Would this group be able to answer some multi arm core and boot loader questions that we have ?
Hi,
I am writing a driver for watchdog timer for my custom platform, what I am observing is, as counter 1st time reaches to zero , then it generates an interrupt and ISR is called
Hello community and experts,
I am having a troubled time to understand the memory barriers. The further I read, the further I am being paranoid about the speculative reads and cpu re-ordering.
I will have some questions and I will really appreciate any…
QBNE (Quick branch not equal)
Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE?
qbeq myLabel, r1, 0
I suppose two if the comparison is false: one is for compare and one is for…
Hello all,
do any of the faster application processors (Cortex-A9 and up) have data trace capabilities enabled in their on-chip debug logic? I have been looking at both Xilinx and Altera Cortex-A9 cores, and both of them appear to only provide instruction…
Hi, expert. I'm making CacheFlush function by Virtual Address.
I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9
I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself…
Dear all,
I am an engineer who is doing signal processing on xilinx FPGAs. I am familiar with C/VHDL/MATLAB. However I want to learn ARM based micro-processors. I know very little about processors and their architecture. Absolutely no practical experience…
For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.
Dear All,
I am new to Arm Processors, I don't know how to start Arm Programming and Application development, can anybody help me? I have working experience on DSP Processor, and Microcontroller, which is the best low cost Arm Processor for personal…
Could anyone give me the code to get the current secure state?
I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.
The CPU boots from an external 4MBytes SPI NOR FLASH chip.
It has 512 KBytes of L2 cache and 32 KBytes…
I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.
hello !
i am houssam an electrical engineering student, i am new to this forum and new for ARM processore i want to make my own PLC (programable logic controler), and i need a processore for to build this PLC, i find a lot of type of ARM processore (cortex…
Hi experts!
As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
But barriers are even used in in-order cpus.
What is for?
Can…
Hi all,
I am working on OrangePi board. The board configuration is,
I have few queries related to Cache memory,
Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…
Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before).
From what I gathered from the documentation of the TZASC and from the…
The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.
I'm trying to access some resources in EL1…
I asked this question in a different community space but it seemed like this is a more appropriate home.
I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…
Hi everyone,
I want to start learning microcontrollers and embedded linux? I want to ask what is differene between A, R and M series of ARM microcontroller? Kindly also suggest me a good book to start learning ARM microcontroller? Which board should I…
Hi,
I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…
The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position is a "1" that means the even is implemented…
Hello all,
I wrote end embedded assembly function for an ARM Cortex A9 (the specific device is Zynq, from Xilinx) as follow
float my_fun(float x)
{
asm volatile ("vdup.f32 d0, r0 \n\t");…
I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…