Hi,
I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"
we can see several information regarding a cache line. Those are:
1. Current data in cache
2. its 4-bit MOESI state,
3. Outer Memory Attribute
4. its tag
5. NS State.
However…
Hi,
I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"
we can see several information regarding a cache line. Those are:
1. Current data in cache
2. its 4-bit MOESI state,
3. Outer Memory Attribute
4. its tag
5. NS State.
However…
Hi all,
I am trying to connect to the RPi2 JTAG.
I have the following setup
- Raspberry Pi 2 running Raspbian 8.0 (Jessie)
- OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.
I setup the GPIO in order to expose the JTAG interface and the…
Hi experts,
I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?
Is it possiable if we make more cores per cluster? if not, what is the limitation?
in arm7tdmi, suppose instruction is being executed and at same time FIQ and IRQ both occur at same time.now according to priority FIQ will be handled then IRQ but my question is that how it will handled IRQ after return from FIQ
i means…
Hi !
I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.
- when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0
From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write…
I'm getting a SIGILL when running a ARMv6 program in a chroot environment.
The instruction that triggers it is
Program received signal SIGILL, Illegal instruction. 0x000104f0 in f () (gdb) disassemble $pc Dump of assembler code for function f: => 0x000104f0…
I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…
Hi,
I'm working on a project which is for debugging cortex-a53 through Jtag interface.
The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…
hi :
I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).
however, I can not find any clue about flushing L2 cache to DRAM(if without L3).
and I saw some points that L2 flushing was not needed.
for ARMv8, how can…
Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!
Hello,
i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..
i have searched a lot but I probaly miss the point.
i want to use data and to transfer data from the processing system to the programable logic section via the amba bus…
As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ
My question is specific to the case when it is only the cacheability…
I find the description below from MMU-500 TRM.
Address width
The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address
bus…
Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to
do some performance profiling.
Hi Experts,
Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?
If it is more specific to A/R/M then its great..
Hello,
Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?
Hi Experts,
Which factor in processor decides whether it can be used in multi-core or not ?
Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?
hi, experts:
I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.
I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.
So, is it only available with Cortex-A9…
Hello all,
I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .
The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.
On Reset, the CPU 0…
Hi,
I just got a raspberry pi 2 and I'd like to play with Trustzone.
People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to
get my hand on the boot of the 4 core A7 CPU, and I managed to boot…
greetings,
as i know the boot loader is the start-up for most of controllers today. till now i just used the boot loader written by someone but i don't have any idea about it how to write it what are the things we have to include and what…
hi,
I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.
Could you give me any suggestion about cache invalid? Thanks!
The program…
In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.
So how can I match them with R0-R14, especially…
Hi Experts,
How to derive the cache memory requirement for the working of the software ?
I could understand that each of the A/M/R processors have its own applications and build with its own Cache size MPU/MMU configurations but how this is derived with…