• GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

    thomas_cp
    thomas_cp

    Hi,

    I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.

    How to test:

    GIC3.0:

    1. read timestamp(t01)

    2. core0 write  ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)

    3. isr in core1, read timestamp…

    • over 2 years ago
    • System
    • Embedded forum
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    thomas_cp
    thomas_cp

    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.

    I am a software engineer.

    My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    This question related to the implementation of the instruction…

    • Answered
    • over 2 years ago
    • System
    • Embedded forum
  • Other core's view after writing ICC_SGI1R_EL1 to trigger SGI

    thomas_cp
    thomas_cp

    For example, the codes are executed in core0.

    codes:

    (1) send SGI to core1 ICC_SGI1R_EL1

    (2) set(a) = 1

    i)  Then the core1 will first see the irq or the change of variable a?

    ii)  If I add ISB between (1) and (2), what happended?

    iii)  If I add DMB (read…

    • over 2 years ago
    • System
    • Embedded forum
  • GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER

    danish259
    danish259

    Is there a way to forward the interrupts from Descriptor to multiple Cores using GICD_IROUTER ?

    Seems the Affinity Routing field in my case is hard-tied to 1.  


    P.S. The SoC I'm working on, do have 8 ARM cores

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • GIC 500 :: Not able to find the definition for GICD_IROUTERn register

    danish259
    danish259

    Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • GIC500 :: Not able to disable Affinity Routing

    danish259
    danish259

    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30.

    Actually I want to forward the interrupt from Distributor to multiple Cores but seems to use ITARGETSR, affinity…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum