How can we route the GICv2 interrupt to the particular core ? ( I have A55 Quard core CPU )
Do we have any example or sample code or any sequence for setting the GIC register ?
Interrupt signal Bypass in GICv2
Hi all,
ARM® Generic Interrupt Controller - Architecture version 2.0
In GICv2 (2.3.1 Interrupt signal bypass, and GICv2 bypass disable --- Page 2-27)
it is mentioned that CPU interface optionally includes Interrupt signal bypass. i have read that concept…
- over 4 years ago
- Open Source Software and Platforms
- Arm Development Platforms forum
Exception handlers and interrupt
Hi All,
i went through this link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
and related a53 vector table implementation.
in this regard, i have a question
1. Say a processor gets stuck in exception handler due…
- over 1 year ago
- System
- SoC Design forum
Finding design errors before it’s too late
What are Design Reviews?
Design Reviews are a service offered by Arm whereby expert engineers visit our partners to perform a detailed review of a particular stage of the design cycle. Based on that review they can provide feedback, best practice advice…
- over 2 years ago
- System
- SoC Design blog
GICv2 How to resolve Multiple Interrupt appearing on a CPU
Hi All,
I am facing issue where, in the event of multiple interrupts on GIC in close vicinity, I am unable to decide on which interrupt has been asserted, to service them properly.
Details:-
This is a simulation Setup.
This is a multicore(4) system with…
- over 2 years ago
- System
- Embedded forum
GICv2 deactivation feature.
Hello all,
There is one thing which is unclear for me in GICv2.
GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a different PE. "
In GICv2 I don't find anything…
- over 2 years ago
- System
- Embedded forum