• MMU and Cache configuration

    ZbinAhmed
    ZbinAhmed

    Hello there,

    I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.

    I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache

    Steps :

    1.Disable cache, branch predictors

    2. Invalidate…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot!

    sam0220
    sam0220

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Turning on MMU and caches on Cortex-A7?

    Juha Aaltonen
    Juha Aaltonen

    In my little program (rpi_stub) it's time to turn on MMU and caches.

    Most of it I seem to have hold of, except cache invalidations.

    In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?

    I understand…

    • Answered
    • over 5 years ago
    • System
    • Embedded forum
  • L1 Cache Eviction Corrupting DDR on A9

    yottaflop
    yottaflop

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support

    BAUDOUIN
    BAUDOUIN

    Hi,

    XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:

      - CAT Cache Allocation Technology

      - CDP Code and Data Prioritization

    Those features are supported by x86 L3 caches. This technology seems to improve performances…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • L2 cache with cortex-A8

    ranchu
    ranchu

    Hello,

    Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ?
    I have some 2 implementation of this routines, one is called L1 and the other L2C-310.

    I am just not sure if using L1 will be good enough, or is it that cortex a8 internal…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Allocation Technology

    sarbojit
    sarbojit

    Hi guys,

    I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache in SOCs

    Ahmed Zafar
    Ahmed Zafar

    Dear Sir/Ma'am,

    In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. 

    I know processors share cache memories with other processors by…

    • over 3 years ago
    • System
    • SoC Design forum
  • shareability attribute for armv8 cortex a-53

    MarekBykowski
    MarekBykowski

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data synchronization Barrier and cache.

    Marcin.Kondraciuk@secom.com.pl
    Marcin.Kondraciuk@secom.com.pl

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 : Cache policy setting

    PrabhuKrishnan
    PrabhuKrishnan

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Registers and Cache on M0

    Sean Dunlevy
    Sean Dunlevy

    Hi,
         Coming from a games coder background, I always seek to find the very limits of what a CPU can do. Now we have PragmatIC and very cheap CPUs but much more importantly - vastly cheaper MROM (Mask ROM). With this in mind, I wanted to know how many registers…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • AMBA AXI CACHE

    srp
    srp

    i am not able to understand working of this CACHE signal pleas explain with simple example.

    thank you!

    • over 2 years ago
    • System
    • Embedded forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 Cache protection

    iuli
    iuli

    Hello all,

    The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Maintenance Transactions

    Taniya Garg
    Taniya Garg

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

    • over 2 years ago
    • System
    • Embedded forum
  • Armv7 Store Buffer

    Yang Wang
    Yang Wang

    Hi,

    Store Buffer holds store operation before it is commited to Cache or Main Memory.

    So only if the proper store buffer entry is drained, can we get the right data by a load operation. Am I right?

    If yes, is it possible that we read a unexpected value…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to handle Cache flush in ACE?

    Taniya Garg
    Taniya Garg

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

    • over 2 years ago
    • System
    • Embedded forum
  • L2 Cache(Pl310) initialisation sequence

    Shravan Alugala
    Shravan Alugala

    Hi ,

    I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

    Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM

    claudiu
    claudiu

    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5?

    Thank you!

    [1] infocenter.arm.com/.../index.jsp

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • 如何把一部分内存数据固定在L2 cache的特定区域呢?

    zhangyumao
    zhangyumao

    请问:

      1. cache(如A53的cache)的配置信息资料可以去哪里寻找呢?

       2. 在裸机状态下如何配置cache的运行模式?

       3. 在os(Android)状态下如何在用户空间配置cache呢?比如把内存中一部分数据固定在L2 cache中的特定区域而不被踢出cache!

    • over 2 years ago
    • 中文社区
    • 中文社区论区
  • Cache ECC in Cortex-R5 & Event bus

    Gael
    Gael

    Hi everybody,

    I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery".

    As far as I understand, in that mode, as the memory…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • ARMv7-A: Cache maintenance operation by VA, performance

    Niklas
    Niklas

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    Jeff Defilippi
    Jeff Defilippi

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

    • over 3 years ago
    • System
    • SoC Design blog
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