Hi
I work with the ARMV8 architecture, I want to disactivate L1 cache ,
to disable the L1 cache I found in the user manual
"" The SCTLR.I bit enables or disables the L1 instruction cache. ""
my question here is: I did not find in the…
Hi
I work with the ARMV8 architecture, I want to disactivate L1 cache ,
to disable the L1 cache I found in the user manual
"" The SCTLR.I bit enables or disables the L1 instruction cache. ""
my question here is: I did not find in the…
Hi everyone,
Is there a way to read the data cache content? I'm using Xilinx SoC ZCU102 evaluation board.
Thanks
Hi,
I was able to view the cache of the armv8 CPU using ARM DS-5. Applying the same steps, i try to view the cache of armv8 CPU using the ARM Development Studio, it throw me an error saying that "Failed to read contents of Internal RAM L1-I_DATA. Please…
Hello.
Does L2 cache data invalidated after finishing each kernel invocation? If not the case, does invalidation depends on memory type (SVM, old buffers, mapped old buffers, etc)?
Question related to Bifrost and Valhall architectures.
Hello. I just found some information about speculative execution and speculative loads/cache line-fills on some ARM processors. Unfortunately I wasn't able to find if any of these present on Cortex-A5. I only saw it has an in-order execution pipeline…
Hello,
I was trying to configure the MPAM system for cache capacity partitioning utilising the fvp base model. I noticed, reading the comments related to the configuration parameters, that the maximum capacity control is not functional, but, anyway, the…
Hi,
I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.
Now I am trying to hook the pagefault…
I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it.
The only documentation I can find for it is a small section in ARM®v7-M Architecture Reference Manual.
Any resources to…
I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it.
The only documentation I can find for it is a small section in ARM®v7-M Architecture Reference Manual.
Any resources…
I'm confused when I see the description of L1 cache:

L1 data memory system:
The L1 data cache is organized as a Virtually Indexed, Physically Tagged (VIPT) cache.
*Note*
In the L1 data memory subsystems, aliases are handled in hardware and from the…
Hi,
I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference between them, for safety reasons; as instance 256KB for…
I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:
char SecretDispatcher[256 * 512];
int counter = 0;
//evicting SecretDispatcher from cache
...
while(counter < (512 * 9 + 1))
{
//evict…I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:
char SecretDispatcher[256 * 512];
int counter = 0;
//evicting SecretDispatcher from cache
...
while(counter < (512 * 9 + 1))
{
//evict…如题,在四核的Arm Cortex-A9中如何测量Core对共享内存访问的开销?最大和最小开销是多少?这里开销具体是指什么?
需要考虑L1 L2 Cache么?最大开销是不是访问主存(不经过Cache)?最小开销是不是从L1 Cache读写?这里需不需要考虑数据量大小?比如对某块内存memset()写一定大小的数据 几K的。。。其最大和最小开销如何测量?
Hi everybody!!
I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).
In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…
Hi at all!
I'm working with TI DM3730 (CortexA8 inside) and an external mobile DDR-SDRAM.
The startup initialize MMU, L1 Cache and L2 Cache and Flow Prediction.
Tests with about 256MiB of data show some data loss when L2 Cache is enabled.
If L2 is disabled…
Hi,
I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…
Dear friend
Cortex-M7 has cache. After enable data cache, will data be stored to cache first when I send a large amount of data continually?
The size of data exceed the space of cache.
Thanks!
Amanda
We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.
From JTAG, Read works properly but writes makes the specific cache line corrupted,
Step 1 : Initial Setup
1. Wrote an application Which runs from…
Hi,
If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written to '0' which is a operation of lots of clock cycles…
Hi,
this question is following my work on the PL310 L2 cache of an imx6 board (see The specified item was not found. ).
We are developing a secure OS that will run alongside Linux. At boot, our secure OS will start a couple application before actually starting…
In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.
To translate this RTL to a revision information, it is stated that
"RTL release 0x9 denotes r3p3 code of the cache controller. See the Release…
Hi !
I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.
- when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0
There is a requirment for me to clean the L1 cache from Linux user space.
There is a DMAC in my SoC platform and this DMAC should read its mirco-code from L2 cache all the time.
When I need to update the DMA mirco-code located in a main-memory, I have two…
From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write…