• Exploring the ARM CoreLink CCI-500 performance envelope - Part 1

    Nick
    Nick

    Introduction

    You may have noticed the ARM announcement last week of a group of Premium Mobile products (if not you can find it here ARM Sets New Standard for the Premium Mobile Experience - ARM) covering a new core processor IP, new GPU IP and a new…

    • over 5 years ago
    • System
    • SoC Design blog
  • Using Portable Stimulus in the Arm World: Creating bare-metal SW coherency scenarios

    Nick
    Nick

    In my last blog (Navigating SoC Verification with Perspec Portable Stimulus) I introduced the Accellera Portable Stimulus Standard (PSS) and how Cadence Perspec System Verifier supports the creation of portable baremetal Arm SoC integration tests using…

    • over 3 years ago
    • System
    • SoC Design blog
  • Is Cache Stashing introduced in DynamIQ similar to IO coherency?

    kangz
    kangz

     IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to go through system interconnect.

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    Jeff Defilippi
    Jeff Defilippi

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

    • over 3 years ago
    • System
    • SoC Design blog
  • Cache and store buffer maintenance in cortex-a8!

    Hamed
    Hamed

    Dear All,

    Technical data sheets for the ARM7500FE  and ARM7100 say that:

    "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected."

    Now the question is that whether…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache maintenance and DMA

    Michael Pulice
    Michael Pulice

    Greetings ARM community,

    I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB.

    As a quick (not perm solution) I used the invalidate all routine.  While obviously not nominal in anyway

    it does allow me…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the Cortex-A12 Main Bus Interface?

    Jin-Hwi Jun
    Jin-Hwi Jun

    Does Cortex-A12 not supprt AMBA4 ACE protocol?

    The figure and description of the Cortex-A12 product page(http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php) shows as if it only supports "AMBA4 AXI Bus" is available bus interface…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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