Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

Hi,

I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

Now I am trying to hook the pagefault…

Hi,

I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a platform with (runs only one OS):

- CCI-400
- A53 Cluster…

The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings

/******************************************************/

6.2.4 Data cache maintenance…

Hi,

I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue.

When I write data(4 bytes aligned) to pcie bar with ioremap_wc, there is some incorrect data. And it is correct…

Hi,

I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

I'm writing bare-metal code, without…

Hi,

I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

My question is how should I interpret the shareability domain: inner, outer…

Hey,

on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2.

Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With an interface function from the API of the PCIe-chip we…

Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…

Hi,

I have a question.

when a processor sends a clean request to data cache, how data cache should behave?

1. does it need to evict all cache lines present in cache (including clean lines) or does it evict only Dirty lines.

2. if dirty lines to write…

Hi,

according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

Hi, 

I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

There is no L3 cache. So the memory…

 IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to go through system interconnect.