• AXI4 Bus Bandwidth/Data Transfer increase

    willo144
    willo144

    Hello,

    I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

    • 2 months ago
    • System
    • SoC Design forum

  • AXI fixed burst to a slave with narrow data width

    Sana
    Sana

    Hi,

    I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

    Would the the data be read from 0x100 only, with data[63:32] always…

    • 9 months ago
    • System
    • SoC Design forum