• questions about APB advantages

    jiunyan jiunyan
    jiunyan jiunyan
    Note: This was originally posted on 8th November 2008 at http://forums.arm.com

    Hi! dear all  :lol:
    Some APB advantages are listed in AMBA 2.0 spec. They are

    "¢ performance is improved at high-frequency operation
    "¢ performance is independent of…
    • over 6 years ago
    • System
    • SoC Design forum

  • ARM Cortex ICode, DCode, System buses

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …
    • over 6 years ago
    • System
    • SoC Design forum

  • How is the PREADY signal triggered low by the Slave in an APB?

    abhisrisai
    abhisrisai

    Hi, 

    I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from  the ACCESS state? 

    If anyone could help me with this basic question, it'll be of great help thank you. :)…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum

  • AMBA

    vish9746
    vish9746

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum

  • Assertion for Multiple Transfer on APB Bus

    Rakesh Venkatesan
    Rakesh Venkatesan

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

    • over 1 year ago
    • System
    • SoC Design forum