Basics: C programming for ARM - AHB transfers

joewu joewu

Note: This was originally posted on 18th September 2007 at http://forums.arm.com

Hello,
Would someone please help me about the next basic things?
I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…

over 6 years ago
System
SoC Design forum

How to go from 32-bit to 64-bit AHB data bus

tamo tamo

Note: This was originally posted on 21st November 2007 at http://forums.arm.com

Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…

over 6 years ago
System
SoC Design forum

Confusion over AMBA AHB hsize[] signal definition

davemac2 davemac2

Note: This was originally posted on 26th February 2008 at http://forums.arm.com

After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface. If an AHB bus is implemented…

over 6 years ago
System
SoC Design forum

AHB Multilayer

Jesuraj vinoth Joseph

Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…

over 6 years ago
System
SoC Design forum

AHB WRAP address boundaries

myarm myarm

Note: This was originally posted on 18th June 2008 at http://forums.arm.com

AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…

over 6 years ago
System
SoC Design forum

AHB Arbiter

vishalrane vishalrane

Note: This was originally posted on 21st November 2008 at http://forums.arm.com

Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?

over 6 years ago
System
SoC Design forum

AHB Busy states...

LEO LEO

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hello guys....

If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?…

over 6 years ago
System
SoC Design forum

app crashes when compiled with OTime O3 using RVDS 4.0

pradipig pradipig

Note: This was originally posted on 1st December 2008 at http://forums.arm.com

Hi,
I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.

My compiler…

over 6 years ago
System
SoC Design forum

AHB split retry response

abc_xyz pqr_def

Note: This was originally posted on 9th December 2008 at http://forums.arm.com

IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
has to to issue…

over 6 years ago
System
SoC Design forum

AHB frequency

vignesharm vignesharm

Note: This was originally posted on 6th January 2009 at http://forums.arm.com

Hi Friends,

My doubt is : what is the maximum AHB clock frequency ?

Regards,
P.Vignesh Prabhu

over 6 years ago
System
SoC Design forum

PL031 verilog generation

nicolan nicolan

Note: This was originally posted on 19th February 2009 at http://forums.arm.com

Pls, I need an answer to a blocking issue

I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't…

over 6 years ago
System
SoC Design forum

In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

Koteswara Rao P

Hi,

In AMBA AHB:-

For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

q) For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

Answered

over 4 years ago
System
SoC Design forum

AHB HREADY low not after address phase

Moish

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

Thanks

Answered

over 3 years ago
System
SoC Design forum

In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

WONG CHENG YEE

I am a Digital Verification Design Engineer.

Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.

I have following questions.

1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

2) From AHB Master side,…

over 3 years ago
System
SoC Design forum