Hi,

I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

So I try to follow that to give the state information.

Cortex-57

JTAG TCK = 3,788MHz.

ARM_STATE_AARCH64 is set

Before Halt state:

EDPRSR = 0x1

EDSCR…

What I'm asking is ARM Architecture Reference Manual for ARMv8-A  says in AArch32 there are two translation table formats:

• Short descriptors: 32 bit
• Long descriptors: 64 bit

On page G4-4726 (Issue B.b), there are various points listed that each…

Hi experts,

I do an experiment about cpu power with a board which has 4 cores of Cortex-A55.

I try to power on/power off core1~3 parallelly.

Sometimes Both PACCEPT and PDENY are zero after changes the power state.

If I only power on/power off one core,…

Dear Experts

I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR…

Hello,

What exactly is the "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ?

I understand the usage model of "first-fault" SVE instrcutions (which is described in many white papers) but the "usage model" of ARMv8…

Hello,

For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0, I found out that the frequency is 8 MHz.

Is this normal? For a target running in GHz?

The target is i.MX8QXP (Quad-Core CortexA35).

I have successfully moved from EL3 to EL2. After doing some initialization I am trying to move from EL2 into EL1 with a very simple guest image. My process looks like:

• Map EL1 memory into EL2
• Copy EL1 image to RAM
• Initialize sctlr_el1 = 0x30d00800

Given a multiprocessor system, how are the PC values of secondary cores set from the primary core? I've read lots of threads stating it can be done but without any details. I could not find anything in the ARMv8 reference manual.

One might contrive…

I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the fact…

In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:

AArch32 
Px 
        PLDW[R1]                     ; preload into cache in unique state 
Loop 
        LDAEX R5, [R1]               ; read…

I have written a library for ARMv8-A 64 bit processors (OS- linaro debian). Now I want to time them. I am utilising gcc compiler and on Intel processors I was timing the execution utilising std::chrono high resolution clock. The issue with arm is, it…

 Dear All,

I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8  processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…

I want to what exactly is arrangement specifier in arm assembly instructions.

I have gone through ARM TRMs and i think if it is size of Neon register that will be used for computation

for e.g. TBL Vd.Ta, {Vn.16B,Vn+1.16B }, Vm.Ta

they mentioned Ta to…

Hey guys,

I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? 

Is it possible from one CPU to access the other CPU's PMU using the memory mapped interface?

Hi,

I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of 

__asm__ volatile ("at s1e1r, %0" : : "r" (buf));    
__asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));