• code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    Hemanth Kumar T
    Hemanth Kumar T

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core?

    RanadeepReddy
    RanadeepReddy

    can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

    how can i know it is booted in 32bit mode?

    Thanks.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm Allinea Studio - 18.2 is now available

    Ashok Bhat
    Ashok Bhat

    We are happy to announce the availability of Arm Allinea Studio 18.2 version with key new enhancements in Compiler and Libraries.

    Arm Compiler now needs a valid license to run

    In 18.2, license management is enabled by default for Arm Compiler. You will…

    • over 2 years ago
    • High Performance Computing
    • HPC blog
  • Changing Exception Level and Security State with an Armv8-A Fixed Virtual Platform

    tmeduthie
    tmeduthie

    In my last couple of blogs we built an ELF image to expose some features of the Armv8-A architecture and toolchain for embedded software development. We got to a point where we could print "hello world" to a telnet console, and enable interrupts on the…

    • changing_exception_level_code.zip
    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Retargeting and Enabling Exceptions with an ELF Image

    tmeduthie
    tmeduthie

    In my last blog we built an executable image to print "hello world" to a terminal. The same tools are being used here. Since the files in this post are a little longer, and consist of a great…

    • retargeting_and_exceptions_blog_source.zip
    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Building an ELF Image for an Armv8-A Fixed Virtual Platform

    tmeduthie
    tmeduthie

    This blog is the first of a short series which will explore the process of writing a program for an embedded system. Here we will use Arm's Compiler 6 toolchain to build an executable image for the AEMv8 Base Platform Model. Both of these are included…

    • building_elf_blog_source.zip
    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Debugging the Armv8-A Linux Kernel with DS-5

    Stephen Theobald
    Stephen Theobald

    To develop, port and debug the Linux kernel on a platform, you will need to be able to set breakpoints, view registers, view memory, single-step at source level and so on - all the normal facilities provided by a debugger.  You may also need to do these…

    • over 2 years ago
    • Software Tools
    • Tools, Software and IDEs blog
  • Arm Technical Training – Any time, any place

    Matt_Rushton
    Matt_Rushton

    Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

    • over 2 years ago
    • Processors
    • Processors blog
  • Assemble a native ARMv8 library, and call Android Java methods from its procedures invoked by an Android App, using the JNI conventions.

    Myy
    Myy

    Purpose

    This document demonstrates how to :
    • write functions (procedures), using the ARMv8 64-bit Gnu AS syntax, that will use the JNI library to call back Java functions from the Android app that called them
    • assemble these procedures into a native library…
    • over 2 years ago
    • Open Source Software and Platforms
    • Android forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • News Round-up: A busy week for the Arm server ecosystem

    Phil Hughes
    Phil Hughes

    If you are following the server or HPC space closely, then you probably have seen the volume of Arm server news go well beyond 11 in the past week. Most of the news is coming straight out of our server ecosystem which has never been more active and robust…

    • over 3 years ago
    • High Performance Computing
    • HPC blog
  • Qualcomm is Bringing an Exciting New Model for Computing, and It’s Built on Arm

    Drew Henry
    Drew Henry

    The center of gravity of compute is moving from a centralized model to being distributed all the way to the edge with trillions of intelligent Arm-powered devices and an Arm-based infrastructure that unlocks their combined potential. Qualcomm’s Centriq…

    • over 3 years ago
    • Processors
    • Processors blog
  • Introducing 2017’s extensions to the Arm Architecture

    Matthew Gretton-Dann
    Matthew Gretton-Dann

    Introduction

    The Arm Architecture is continually evolving, and this blog gives a high-level overview of some of the changes made in Armv8.4-A*. We develop these changes by listening to the Arm Ecosystem and working with them to provide new functionality…

    • over 3 years ago
    • Processors
    • Processors blog
  • Migrating High Performance Applications to the Armv8-A Architecture

    Patrick Wohlschlegel
    Patrick Wohlschlegel

    In recent months, the HPC market has been waiting to see how Arm will drive innovation for High Performance Computing. Arm and its partners have been working hard to enable a greater variety of competitive hardware solutions, providing the innovation…

    • over 3 years ago
    • High Performance Computing
    • HPC blog
  • How to create jump-tables in Armv8 Arm32 assembly language?

    AnthonyPaulO
    AnthonyPaulO

    I've been learning Arm32 assembly on my Raspberry Pi recently and all is going well but I would like to create a jump table and have no idea how. The bl (branch and link) instruction needs an address label, but I would like to simulate a switch statement…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TTBR1_EL1 aligment

    Vincent Siles
    Vincent Siles

    Hi !

    I'm struggling a bit to understand the alignment constraints on the physical address we put in TTBR1_EL1. The ARM ARM v8 doesn't give a precise link in TTBR1_EL1 description to where is alignment is defined. For this post, I'm using a 4k granule…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm and Packet work to speed Armv8-A access for developers

    Jeff Underhill
    Jeff Underhill

    The Open Source community has been busy at work targeting Arm based infrastructure platforms as evidenced by the tens of thousands of packages already available via traditional distribution channels from Debian, Ubuntu, OpenSUSE, SUSE, fedora, CentOS, FreeBSD, 

    …
    • over 3 years ago
    • High Performance Computing
    • HPC blog
  • Is it possible the direct device's interrupt assignment to the guest OS instead of being routed by the hypervisor to the guest OS?

    Jorge
    Jorge

    Hi everyone,

    I'm currently working with devices virtualization and I have noticed on my experiments that one of the most sources of overhead comes from the device's interrupts, even if the guest OS has a pass-through access. This is due to the fact of…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • VMSAv8-64 - How to change 2-stage translation table descriptors of a given VMID and do invalidation afterwards?

    Jorge
    Jorge

    Hello everyone,

    Basically, I have a setup in which an hypervisor is running in EL2 and two guestOS running in EL1/EL0, being one a special guest (able to perform requests to the hypervisor), and the other one a limited guestOS. In ARMv8, each guest OS…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the relationship between exclusive access and memory cacheable in Cortex A53?

    Emmy0
    Emmy0

    Hello community and experts,

             I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

             When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Transition to secure monitor flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMC flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Transition to secure monitor flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A的SP_EL0的安全?

    chendader
    chendader

    在ARMv8-A中,EL1/2/3除了可以自身的堆栈寄存器SP_ELn以外,还可以使用SP_EL0。

    与此同时EL0也可以使用SP_EL0。

     我想在EL0的应用程序应该可以通过SP_EL0,访问到EL1/2/3的数据,这岂不是不安全?

    希望帮忙解答,谢谢!

    • over 3 years ago
    • 中文社区
    • 中文社区论区
  • How to ensure the safety of SP_EL0

    chendader
    chendader

    Hi experts,

    In ARMv8, EL1/2/3 can use either their own stack pointer, SP_ELx or SP_EL0.

    SP_EL0 can be used in EL0.

    why it is safe to use SP_EL0 in EL1/2/3?  I think the applications in EL0 may get the data of kernel in EL1 through SP_EL0.   

    Can anybody…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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