Hi everyone ,
I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).
My project is to develop a simple OS, but I met a problem:
When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…
On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?
Hi,
I'm using DMA transfering data through ACP on A53.
According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?
Then software must re-configure DMA then re…
HI,
Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?
I want to read the flags with no jump (and it is critical).
Thanks
The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…
A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?
The simple answer to this is – the power budget…
