Hello,
I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault.
Current steps which i am doing are:
1) inside kernel space, allocating 2 pointers (say p, q) and allocating…
Hi,
I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".
So I try to follow that to give the state information.
Cortex-57
JTAG TCK = 3,788MHz.
ARM_STATE_AARCH64 is set
Before Halt state:
EDPRSR = 0x1
EDSCR…
I have written a library for ARMv8-A 64 bit processors (OS- linaro debian). Now I want to time them. I am utilising gcc compiler and on Intel processors I was timing the execution utilising std::chrono high resolution clock. The issue with arm is, it…
I asked this question in a different community space but it seemed like this is a more appropriate home.
I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…
The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…
Two questions:
1. Where can I find the detailed explanation of ARM PMU events?
2. How to know the stall cycles for e.g. icache miss etc.?
Thanks.
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…
Hi Experts,
What are all the list of integrated debug functionalities in ARM v8 which will be affected by the cold and warm resets.
Regards,
Techguyz
I'm an arduino guy looking for more power and I'd like to start using the high performance ARM chips such as the A57 and soon the A75, but I'm having an impossible time finding dev boards for anything other than some older ARM chips (I think the highest…
I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…
Hi,
I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.
The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.
There is no L3 cache. So the memory…
Hi Experts,
Please specify is there any document on the Cortex A series comparison sheet for the various properties.
For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…
Hi,
I am fairly new to ARM processor and start work with cortexA57 recently. After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.
1. How does the exception level change from one to…
This white paper is an introduction to porting existing code to the A64 instruction set supported by Armv8-A processors like the Cortex-A53 and Cortex-A57 from Arm. It will also be useful for those writing new code for these platforms.
We are interested in developing Board Support Package and Bootloader code for SOCs based on ARMv8 Architecture (A57/A53). Can someone please suggest is Juno Board a good option for it?
We are interested in writing the BSP code for Memory Controller, UART…
With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…
The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…
A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?
The simple answer to this is – the power budget…
