Hello 

I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

MRS X0, HCR_EL2
AND X0, X0, 0xFFFFFF…

Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

Hello,

For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0, I found out that the frequency is 8 MHz.

Is this normal? For a target running in GHz?

The target is i.MX8QXP (Quad-Core CortexA35).

Hi,

ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

Thanks…