Hi All,

What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

Regards

Nitin

I asked this question in a different community space but it seemed like this is a more appropriate home.

I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…

The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…

Hi everyone ,

I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

My project is to develop a simple OS, but I met a problem:   

When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

Hi,

I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

I have written an exception…

Hello experts,

I have come to having a question.
VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
The software can be downloaded from the following link…

Hi experts,

I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

Is it possiable if we make more cores per cluster? if not, what is the limitation?

I find the description below from MMU-500 TRM.

Address width

The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

bus…

Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

do some performance profiling.

Where can i get a list of all these family of ARM processors and their differences

On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

Two questions:

1. Where can I find the detailed explanation of ARM PMU events?

2. How to know the stall cycles for e.g. icache miss etc.?

Thanks.

In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

I think the cortex-A7 has 8-stage pipeline, the PC value is also current+8(this is back-forward for old design), but…

Hi,

I was using following method to read clock in cortex-a15:

       static void readticks(unsigned int *result)

        {

            struct timeval t;…

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

     STR R0, [Msg]

     STR R1, [Something…

Hi,

    I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…

Hi Experts,

                    I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

I could…

GIC-500 how connects to CPU cores?

在GIC-500 中CPU Interface 是GIC的一部分还是cluster 的一部分？

Hi Experts,

Does it possible to invoke the application running in EL0 directly from the hypervisor EL2 without giving control to EL1 ?

Regards,

Techguyz

Hi Experts,

What are all the list of integrated debug functionalities in ARM v8 which will be affected by the cold and warm resets.

Regards,

Techguyz

Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

In our watch point handler, we first disabled watch point control, then handle debug…