MPAM cache partitioning support in FVP base model

Matteo Zini

Hello,

I was trying to configure the MPAM system for cache capacity partitioning utilising the fvp base model. I noticed, reading the comments related to the configuration parameters, that the maximum capacity control is not functional, but, anyway, the…

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Cache clean of translation tables stops execution?

Richard Kraus

Hi,

I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

Now I am trying to hook the pagefault…

Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Yeo Reum Yun

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

STR R0, [Msg]

STR R1, [Something…

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Which ARMv8 register controls cache partitioning

rudyjantz

Hi ARM folks,

Which register controls the cache partitioning behavior on ARMv8 chips?

My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning schemes. ThunderX are ARMv8 chips, as mentioned here…

I want to know how to invalidate or clean to cache only used secure-world

박주병

Hello experts.

I making a security operating system using trustzone using ARMv8 big-little core.

I face some probleam of cache clean or invalidate.

I want to cache flush to used only secure-world memory based on virtual memory, no flush non-secure world…

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