Synchronization Between CortexA and CortexM

M.Eladouly

Hello,

I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4).

Currently, I use Load/Store executive assembly instructions along with memory attributes for the MMU to synchronize between the CortexA…

Answered

no C bit in SMMU_CBn_SCTLR

Jerry

I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.

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TrustZone environment for ARMv8-M?

loquat3

I want to work the TrustZone program for ARMv8-M.
Is there TrustZone environment for ARMv8-M? (ex. software emulator.)
I used Foundation_Platformpkg for ARMv8-A.
Similar environment is available?

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Correct way to mask interrupts in secure world ARMv8M M33

raghu.ncstate

Hello,

I'm wondering what the correct way to mask non secure interrupts is, on entering secure world on an ARMv8-M processor, with Main and Security extensions. The scenario I have is as follows:

The SOC has 1 M33 core. I have a non secure OS that…

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How to run TF-M on keil M23/M33 fvp?

matt-ma

I have noticed there are also M23/M33 fvps under Keil IDE related path. Whether there is some difference about the startup parameters to run TF-M on Keil fvps compared to DS-5 fvps?