• dsb and dmb

    digital_kevin
    digital_kevin

    Hi all:

    I have some questions about DMB and DSB in armv8.

    (1)

    In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

    But in ARM Cortex-A…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum

  • Enable MMU and d-cache on ARMv8 for u-boot

    pkumar25
    pkumar25

    Hi,
    This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
    "Synchronous Abort" handler…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Transition to secure monitor flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Introducing 2017’s extensions to the Arm Architecture

    Matthew Gretton-Dann
    Matthew Gretton-Dann

    Introduction

    The Arm Architecture is continually evolving, and this blog gives a high-level overview of some of the changes made in Armv8.4-A*. We develop these changes by listening to the Arm Ecosystem and working with them to provide new functionality…

    • over 2 years ago
    • Processors
    • Processors blog

  • Transition to secure monitor flow on ARMv8

    Umair Khan
    Umair Khan

    Hi everyone,

    Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

    In ARM v8 vector table, given on ARMv8-A architecture…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • How to understand ARMv8 'SEVL' instruction in spin-lock?

    yan.wy
    yan.wy

    hi experts,    

        ARMv7 spin-lock use 'WFE' instruction to wait for lock release and use 'SEV' in spin-unlock to notify all cores.   

        but ARMv8 use 'SEVL; WFE' instructions in spin…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Purpose of EL0 EL1 ..

    techguyz
    techguyz

    Hi all,

    ARMV8 has number of exception levels as EL0 , EL1, EL2, EL3 .. How this is managed and what is the exact use case of the same ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Generic Timer - Is it optional?

    techguyz
    techguyz

    Hi all,

    The generic timer feature is provided in the V8 manual. Is it optional like GIC or it will be available with processor IP by default like cache, MPU features. Is it operates on CPU clock or it requires separate clock source ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • Cryptography instructions sample for ARMv8

    chinatiger
    chinatiger

    hi, experts:

    I found ARMv8 supported some cryptography instructions.

    So:

    Is there any sample code demonstrating how to use these crypto instructions?

    best wishes,

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum

  • 飞腾芯片亮相国际高性能微处理器研讨会

    wangyong
    wangyong

    来源： 中国经济网   发布者：中国经济网

    时间：2016年8月24日 06:07

    中国经济网 北京8月23日讯(记者赵槿)美国旧金山时间8月22日上午,第28届国际高性能微处理器研讨会(Hotchips-28)在美国硅谷的库比蒂诺隆重召开,来自中国天津飞腾信息技术有限公司的FT-2000/64中国芯片和FT-2000服务器样机在现场引起极大关注。

    　　飞腾去年曾在Hotchips-27上介绍了Mars(火星)芯片的技术细节,业界反响强烈。时隔一年,Mars露出了庐山真面目,飞腾在ARM全球用户大会以及Hotchips大会上展示了芯片样片及服务器样机…

    • over 3 years ago
    • 中文社区
    • 中文社区博客

  • [新闻稿]ARM为高端移动体验树立全新标杆

    Song Bin 宋斌
    Song Bin 宋斌

    新闻要点:

    ·         基于ARMv8-A架构的最新处理器ARM® Cortex®-A72，性能较五年前的处理器提升50倍

    ·         最新ARM CoreLink™ CCI-500高速缓存一致性互连（Cache Coherent Interconnect）允许更大的系统带宽…

    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • The ARMv8-A architecture and its ongoing development

    David Brash
    David Brash

    ARMv8-A, the ARMv8 A-profile version of the ARM architecture, was first publicly previewed in October 2011. Over the past two years, there have been a growing number of ARMv8-A announcements from ARM, such as its Cortex-A53 and Cortex-A57 products, plus…

    • over 5 years ago
    • Processors
    • Processors blog

  • ARM遊戲開發者日 -- 與中國遊戲開發者的技術交流盛會

    Alan Chuang
    Alan Chuang

    遊戲對繪圖處理器(GPU)來說一直是主要的應用之一， 更不用說在智慧行動裝置上大部分的應用程式收入都來自於遊戲類程式。這也是為什麼ARM今年在一些主要的城市舉辦遊戲開發者日的活動。中國是三大手游市場之一，所以在中國舉辦遊戲開發者日的原因也就不在話下。今年在中國的技術交流盛會，我們選擇在中國西部最大的城市, 也是四川的首府成都舉辦，並且很榮幸地和成都移動互聯網協會一起合作。這次活動的地點也很關鍵 - 選擇在成都天府軟件園裡的愛糖咖啡舉辦。成都天府軟件園是中國著名的高科技園區之一，也讓園區的工程師方…

    • over 5 years ago
    • 中文社区
    • 中文社区博客

  • Critical interrupts

    Michael Williams
    Michael Williams

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…

    • over 5 years ago
    • Processors
    • Processors blog