Greetings,
If I leave the FVP idle for around 1 hour and come back to it, I find that it freezes and have to stop the simulation and re-run it again. What is the possible reason for this and is there a way to stop that from happening? Thank you for your…
Hello,
I am a PhD student doing research using the ARMv8 hardware features. I have a few questions regarding them. Some of these may seem a bit trivial, but I like to be a bit more thorough and confirm my understanding, and ARM is relatively new to me…
I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.
I tried -mfpu…
Dear experts,
I see a lot of code in opensource like
.macro disable_daif msr daifset, #0xf .endm
and it doesn't apply ISB instruction after it. Though I read in ARM manual that:
"context-changing operations
that require the insertion…
Hi,
I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".
So I try to follow that to give the state information.
Cortex-57
JTAG TCK = 3,788MHz.
ARM_STATE_AARCH64 is set
Before Halt state:
EDPRSR = 0x1
EDSCR…
I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the fact…
I wonder how VA->PA translation is handled from non-secure world with Aarch64.
I see the HYP mode uses IPA so that the second stage translation may restrict the VM to certain memory.
But what about limiting access to secure memory? Is it only possible…
Hi,
The latest 64-bit architecture can on both AArch64 and AArch32 state.
Can someone tell me how to utilize this feature so that I can seamlessly integrate algorithms (which are optimized with 32-bit and 64-bit instructions) with applications which are…
Hi everyone ,
I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).
My project is to develop a simple OS, but I met a problem:
When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…
Hi,
I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.
I have written an exception…
Hello experts,
I have come to having a question.
VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
The software can be downloaded from the following link…
Hi Experts,
ARMv8 MMU TTBRn_ELx registers are banked by exception level.
In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1
and Non-secure…
On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?
Hi, ARM experts:
When we porting a secure os in 32bit mode in v8 secure EL1(our EL3 is running in AARCH 64bit mode), we got a strange problem:
When start booting secure os in secure EL1, the bootstrap code…
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…
Hi experts,
i am trying wakeup the secondary CPU core in bootloader, i am able to do this through a trusted firmware. The problem comes after wakeup!
Once the cpu is up it will be in EL-2 mode and it executes a predefined function…
Hi Experts,
I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.
I could…
Hi ARM expert,
In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…
It can see almost 100% CPU0 usage during the timeline 2.34s ~ 2.42s(in figure 1). How can we know which functions are executed in CPU0/ CPU1 @timeline 2.376s(in figure 2)?
The figure 3 is show the functions sheet @timeline 2.376s, but no more information…
Hello everyone,
Basically, I have a setup in which an hypervisor is running in EL2 and two guestOS running in EL1/EL0, being one a special guest (able to perform requests to the hypervisor), and the other one a limited guestOS. In ARMv8, each guest OS…
Please clarify that with me... With
"The current Program Counter (PC) cannot be referred to by number as if part of
the general register file and therefore cannot be used as the source or destination
of arithmetic instructions, or as the base, index…
Hi,
I am fairly new to ARM processor and start work with cortexA57 recently. After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.
1. How does the exception level change from one to…
Hi,
I've heard that the cost of implementing a register is more.
In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?
Hi everyone!
I want to set and then trap EL1 hardware breakpoints to EL2. I didn't perfectly understand if such an action is possible at all. In some places the documentation said that MDCR_EL2.TDE enables *Software Breakpoints* trapping to EL2, but on…
