• Embedded ARMv8 dev board

    AnthonyPaulO
    AnthonyPaulO

    I'm an arduino guy looking for more power and I'd like to start using the high performance ARM chips such as the A57 and soon the A75, but I'm having an impossible time finding dev boards for anything other than some older ARM chips (I think the highest…

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • How to implement saturation instructions in ARMv8 architecture?

    Natesh Raina
    Natesh Raina

    Is there a way to write an equivalent of 32-bit saturation instruction such  as QADD or QSUB without using neon saturation instructions for Armv8 architecture?  

    • Answered
    • over 3 years ago
    • System
    • Embedded forum
  • how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"?

    astonelin@gmail.com
    astonelin@gmail.com

    ARMv8 introduces this new attribute of memory type. (B2.8.2)

    And also it recommends that "early write acknowledgement" attribute should be exported to interface between PE and interconnect fabric. (J4.1.1)

    However, there is no any clue about…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Running armv7 binaries on armv8

    Veeranna
    Veeranna

    Hi Experts,

    I have binaries built for armv7 architecture, without rebuilding binaries can I run on armv8?. I think its possible, but wanted confirm is there any limitation?

    Thanks,

    Veeranna

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Armv8 Memory Mapping

    AnthonyPaulO
    AnthonyPaulO

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • About watch point debug excption on Cortex-A53

    tao.zeng
    tao.zeng

    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

    In our watch point handler, we first disabled watch point control, then handle debug…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Initial page table walk for secure/nonsecure accesses

    KamGators
    KamGators

    I have a basic concept question.  From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups.  So these can be used to block access ... I.e. NS access is attempting…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trust Zone and Virtual Machines / KVM

    Sreekumar
    Sreekumar

    Is it possible to for a Virtual Machine to switch the processor to the secure state ?

    I have a Linux virtual machine hosted by KVM hypervisor . I plan to run the  WPA2 authentication and other crypto functions in the secure world.  Is this possible in ARMv8A…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the difference between LDAXR and LDREX

    Aquila
    Aquila

    Hi experts:

    In armv8 specification, I have found two types of exclusive access instructions: LDAXR/STLXR and LDREX/STREX. I have some questions about these instructions:

    (1)  What's the difference between these exclusive access instructions?

    (2) Is…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Virtualizing GICv2.

    Jorge
    Jorge

    Hi all,

    I'm currently virtualizing the GICv2 and some doubts came out during its design. Scenario encompasses the same instance of an hypervisor running in two different CPUs (CPU0 and CPU1). Also, There is one guest running on top of two vCPUs. Each…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • armv7a/armv8 : Undefined Abort Exception and MMU

    Vincent Siles
    Vincent Siles

    Hi !

    When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?

    Best,

    V.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8: strongly ordered memory and exclusive access

    Vincent Siles
    Vincent Siles

    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

    While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode

    RanadeepReddy
    RanadeepReddy

    excuse me for my English!!!

    i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

    i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • help me to understand this assembly program for configuring MMU for ArmV8,A53.

    RanadeepReddy
    RanadeepReddy

    ******************************************************************************/
    /*****************************************************************************/
    /**
    * @file translation_table.s
    *
    * @addtogroup a53_32_boot_code
    * @{
    * <h2> translation_table…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A CurrentEL Register Definition

    kuksho
    kuksho

    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

    . How does the PSTATE bits map to CurrentEL ?

    I read somewhere that a CurrentEL value of 0x4 denotes EL1…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Multi core L1 cache coherent

    Jorney
    Jorney

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indirect branches in ARMv8

    MarekBykowski
    MarekBykowski

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 mmu problem

    bug57520
    bug57520

    Hi ARM experts,

    I have a problem in using armv8 mmu in bare-metal system:

    When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.

    In Armv8 ARM page D4-1744, table lookup starts at level 0.

    Is the Level 0 table…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which register are dedicated for each MPCore in ARMv8-A architecture?

    StanleyDDD
    StanleyDDD
    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature Comparison ARM v8 series

    techguyz
    techguyz

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Confusion about exception level of ARMv8

    Xinwei
    Xinwei

    Hi,

    I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

    1. How does the exception level change from one to…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 AArch64: trapping hardware breakpoint to EL2

    meitarb
    meitarb

    Hi everyone!

    I want to set and then trap EL1 hardware breakpoints to EL2. I didn't perfectly understand if such an action is possible at all. In some places the documentation said that MDCR_EL2.TDE enables *Software Breakpoints* trapping to EL2, but on…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What exactly is a full implementation of ARMv8.2-A?

    khunter
    khunter

    The technical spec for ARM Cortex A-75 claims that it supports a full implementation of ARMv8.2-A. The documents I have been able to reference only point to ARMv8A. Specifically I'm looking for what ARMv8.2-A brings to the SIMD table other than fp16 arithmetic…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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