• Developments in the Arm A-Profile Architecture: Armv8.6-A

    Nigel Stephens
    Nigel Stephens

    The Arm Architecture is continually evolving to meet the needs of our ecosystem partners. This blog gives a high-level overview of some of the changes being introduced in Armv8.6-A.

    The enhancements to the architecture provide more efficient processing…

    • over 1 year ago
    • Processors
    • Processors blog
  • Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

    Branden Sherrell
    Branden Sherrell
    I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the fact…
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 memory ordering

    roffelsen
    roffelsen

    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:

    AArch32 
    Px
            PLDW[R1]                     ; preload into cache in unique state
    Loop
            LDAEX R5, [R1]               ; read…
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Getting Execution Time of progams on armv8_64-bit processors

    abhi.verma
    abhi.verma

    I have written a library for ARMv8-A 64 bit processors (OS- linaro debian). Now I want to time them. I am utilising gcc compiler and on Intel processors I was timing the execution utilising std::chrono high resolution clock. The issue with arm is, it…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Obtain CPU Temperature in Kernel

    zzT
    zzT

     Dear All,

    I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8  processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • BFloat16 processing for Neural Networks on Armv8-A

    Nigel Stephens
    Nigel Stephens

    Neural Networks are a key component of Machine Learning (ML) applications. Project Trillium, Arm’s heterogeneous ML platform, provides a range of technologies in this field, including instructions that accelerate such applications running on CPUs based…

    • over 1 year ago
    • Processors
    • Machine Learning IP blog
  • What is arrangement specifier(.16b,.8b) in ARM assembly language instructions?

    surajrgupta
    surajrgupta

    I want to what exactly is arrangement specifier in arm assembly instructions.

    I have gone through ARM TRMs and i think if it is size of Neon register that will be used for computation

    for e.g. TBL Vd.Ta, {Vn.16B,Vn+1.16B }, Vm.Ta

    they mentioned Ta to…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 PMU access

    Jorge
    Jorge

    Hey guys,

    I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? 

    Is it possible from one CPU to access the other CPU's PMU using the memory mapped interface?

    …
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • determine a page size on armv8

    MarekBykowski
    MarekBykowski

    Hi,

    I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of 

    __asm__ volatile ("at s1e1r, %0" : : "r" (buf));    
    __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));

    …
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?

    Nitin Bhaskar
    Nitin Bhaskar

    Hi All,

    What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

    Regards

    Nitin

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A:TrustZone and MMU

    42Bastian
    42Bastian

    I wonder how VA->PA translation is handled from non-secure world with Aarch64.

    I see the HYP mode uses IPA so that the second stage translation may restrict the VM to certain memory.

    But what about limiting access to secure memory? Is it only possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • I'm not seeing any flush-to-zero (FTZ) effects with NEON intrinsics on an ARM A9, any advice?

    David L
    David L

    Hi everyone,

    As the title states - I've had issues reproducing flush-to-zero (FTZ) using the NEON intrinsics provided in the 'arm_neon.h' header. For test purposes I'm using an iPhone 6 with an ARMv8-A dual-core ('Twister') CPU.…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure Cortex-A57 PMU

    Michael
    Michael

    I asked this question in a different community space but it seemed like this is a more appropriate home.

    I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use generic timer/counter

    Michael
    Michael

    The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to do the ARM state change between 64-bit and 32-bit?

    Prasad
    Prasad

    Hi,

    The latest 64-bit architecture can on both AArch64 and AArch32 state.

    Can someone tell me how to utilize this feature so that I can seamlessly integrate algorithms (which are optimized with 32-bit and 64-bit instructions) with applications which are…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to return from exception generated by SMC instruction

    rajtx
    rajtx

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A Instruction for Getting CPU Number

    Shengye Wan
    Shengye Wan

    Hi,

    I'm using a Juno r1 board and I'm trying to get processor's related CPU ID without using any header file like function sched_getcpu from sched.h.

    The reason is I want to get the CPU number for TrustZone application and there is no way to…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why there are 4 cores per cluster in ARMV8 architecture

    RadarSong
    RadarSong

    Hi experts,

    I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

    Is it possiable if we make more cores per cluster? if not, what is the limitation?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why the address width of MMU-500 is different with Cortex-A53/57?

    wangyong
    wangyong

    I find the description below from MMU-500 TRM.

    Address width

    The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

    bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARM have a time counter mechanism?

    Cyberman Wu
    Cyberman Wu

    Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

    do some performance profiling.

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene?

    Moix
    Moix

    Where can i get a list of all these family of ARM processors and their differences

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Minimum MMU table size on ARMv8 to map 4GB memory space, in AArch64 mode

    yifanfeng
    yifanfeng

    On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • where can I find the detailed explanation of ARM PMU events?

    alexamy
    alexamy

    Two questions:

    1. Where can I find the detailed explanation of ARM PMU events?

    2. How to know the stall cycles for e.g. icache miss etc.?

    Thanks.


    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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