• Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?

    George_
    George_

    Hello:

    Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess on executing an exception return operation in EL1, which…

    • Answered
    • 10 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Rowhammer bug on ARM

    Frederick
    Frederick

    Is there anyone who is working or having background knowledge on the rowhammer bug on ARM-based devices ?

    Thank you.

    • 11 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Parallel heterogenous computing for IoT-boards and nanocomputers with Armv8 and AArch64 hardware architecture

    Arthur Ratz
    Arthur Ratz
    This is a guest blog contribution from Arthur Ratz

    Build and run a modern parallel code in C++17 and CL and SYCL programming model specification on the IoT-boards and innovative tiny-sized nanocomputers. These are based on the revolutionary cluster…

    • 11 days ago
    • Processors
    • Processors blog
  • How can I trigger an SError exception on a cortex A processor

    Awax
    Awax

    Is there a reproducible way of intentionnaly triggering a SError on a cortex A implementation (CortexA53 for example),
    I need this to implement handlers for different errors and I need this to test my implementation.

    THanks.

    • 12 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disable Cache L1 et L2 Armv8

    Rifakst
    Rifakst

    Hi

    I work with the ARMV8 architecture, I want to disactivate L1 cache ,

    to disable the L1 cache I found in the user manual
    "" The SCTLR.I bit enables or disables the L1 instruction cache. ""

    my question here is: I did not find in the…

    • Answered
    • 14 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to disable the branch prediction on armv8

    Rifakst
    Rifakst

    Hello,

    I am working with ARMV8 Cortex A72 architecture,
    i want to know can i turn off branch prediction?
    and how can i do it?

    best regards,

    • 18 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Rowhammer bug on ARMv8

    Frederick
    Frederick

    Hi Everyone,

    I have been trying exploiting Rowhammer bug on ARMv8 running linux for a university project.

    The device is a Quad core Cortex-A72 (ARM v8) 64-bit SoC @ 1.5GHz.

    First i checked the UCI bit value in the SCTLR register, and is set. So the unprivileged…

    • 2 months ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Arm A-Profile Architecture Developments 2020

    Martin Weidmann
    Martin Weidmann

    Working with its architecture licensees and ecosystem partners, Arm continues to evolve its architecture, developing new functionality to meet the needs of both new and existing markets.

    This blog discusses some of the key additions to the A-profile architecture…

    • 2 months ago
    • Processors
    • Processors blog
  • How to set up stage-2 translation table

    irakatz
    irakatz

    Hi,

    I am trying to enable stage-2 translation for Armv8 aarch32, cortex-a53. If I set HCR.VM=1(enable stage-2 translation) it will crash. I suspect it does not set up stage-2 translation table. But when I read the Arm Architecture Reference Manual, I…

    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • DRAM address mapping on a Cortex-A72 ARMv8

    Frederick
    Frederick

    HI Everyone,

    I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ?
    is there any bit to check for it ?

    Thank you.

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Core_n System Timer reset behaviour

    Helmy Mohamed
    Helmy Mohamed

    Hello, 

    I'm working with i.MX8DX (Dual Core CortexA35) 

    My question is this:

    If a PE is reset. Is the CNTPCT_EL0 is also reset and start from 0? or keep counting normally?

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • How Can I Synchronize the Generic Timer values in different PEs in the same Core?

    Helmy Mohamed
    Helmy Mohamed

    Is the timer values in CNTPCT_EL0 in each PE in the same core are synchronized? and if not how can I do so?

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Time measurements ARM v8 platform running Linux

    Frederick
    Frederick

    HI Everyone,

    This is my first time here.

    I need help about time measurements on a Cortex-A72 (Arm v8) 64-bit.

    I have been trying to read the cycle counter (i have got root privileges on machine), but i can't.

    my c code:

    #define _GNU_SOURCE
    #include…

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • trustzone memory configuration for cortex-A57

    raks8877
    raks8877

    Hello,

    I am using jetson tx2 development board which has arm cortex a57 processor which uses arm trusted firmware(atf) to boot. Trusty is the secure world operating system provided by atf.

    Following are my questions:

    1) How to configure how much ram…

    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Neoverse N1 microarchitecture ISA support

    Mohannad Ismail
    Mohannad Ismail

    Greetings,

    I have a few questions regarding the Neoverse N1. According to the specifications, it mainly uses the ARMV8.2 ISA. However, there is possible support also for other instructions in other ISAs such as v8.4, v8.5 and cryptographic extensions…

    • Answered
    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • translation table APTable permission problem

    raks8877
    raks8877

    Hello,

    I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault.

    Current steps which i am doing are:

    1) inside kernel space, allocating 2 pointers (say p, q) and allocating…

    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Priority Drop and Deactivation Interrupts at EL2

    Helmy Mohamed
    Helmy Mohamed

    Hello 

    I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

    I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

    MRS X0, HCR_EL2
    AND X0, X0, 0xFFFFFF…

    • 5 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Measuring performance of programs on the FVP

    Mohannad Ismail
    Mohannad Ismail

    Is the FVP accurate in terms of measuring performance of programs? Is it cycle accurate? If I use clock_gettime to measure time taken on applications, is it meaningful? If not, is there an accurate way to measure performance of programs on the FVP?

    • Answered
    • 5 months ago
    • Tools and Software
    • Simulation Models forum
  • MPAM cache partitioning support in FVP base model

    Matteo Zini
    Matteo Zini

    Hello,


    I was trying to configure the MPAM system for cache capacity partitioning utilising the fvp base model. I noticed, reading the comments related to the configuration parameters, that the maximum capacity control is not functional, but, anyway, the…

    • Answered
    • 5 months ago
    • Tools and Software
    • Simulation Models forum
  • System wide cache flush

    M. Elsayed Badawy
    M. Elsayed Badawy

    Hello,

    I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

    My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

    • Answered
    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Enabling top-byte ignore on ARMv8 Base FVP

    Mohannad Ismail
    Mohannad Ismail

    Greetings,

    I would like to enable top-byte ignore support on the FVP. I would be grateful on any guidelines on how to do that. Thank you very much!

    Best regards,

    Mohannad Ismail

    • 6 months ago
    • Tools and Software
    • Simulation Models forum
  • ARM Base FVP freezes if left idle

    Mohannad Ismail
    Mohannad Ismail

    Greetings,

    If I leave the FVP idle for around 1 hour and come back to it, I find that it freezes and have to stop the simulation and re-run it again. What is the possible reason for this and is there a way to stop that from happening? Thank you for your…

    • 6 months ago
    • Tools and Software
    • Simulation Models forum
  • Cache clean of translation tables stops execution?

    Richard Kraus
    Richard Kraus

    Hi,

    I am currently working on an integrity enforcer running in a modified version of the ARM trusted firmware in EL3. To gain access to the memory I added 4 1GiB entries to the translation tables located in the TTBR0_EL3.

    Now I am trying to hook the pagefault…

    • 6 months ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Debugging on ARM Base FVP

    Mohannad Ismail
    Mohannad Ismail

    Hello,

    I would like to know how do I attach gdbserver to my ARM Base FVP for debugging. All tutorials online explain using DS-5. I would like to use gdb since I am more comfortable with it. I already enabled networking on my FVP.

    Thanks for your help…

    • Answered
    • 6 months ago
    • Tools and Software
    • Simulation Models forum
  • Debugger cannot execute cast and vectorization commands

    Rei
    Rei

    Hello. I am a novice in programming. I have a problem with the debugger.
    My target CPU is Cortex-A72 Aarch64, FPU Armv8 (Neon). I use vectorization.
    When the debugger reaches the line:
    uint8x16_t aa = vmovq_n_u8 (0);
    he writes that it is running, but nothing…

    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
>